From: Krzysztof Kozlowski <krzk@kernel.org>
To: John Madieu <john.madieu.xa@bp.renesas.com>
Cc: claudiu.beznea.uj@bp.renesas.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org,
geert+renesas@glider.be, krzk+dt@kernel.org, robh@kernel.org,
bhelgaas@google.com, conor+dt@kernel.org, magnus.damm@gmail.com,
biju.das.jz@bp.renesas.com, linux-pci@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, john.madieu@gmail.com
Subject: Re: [PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
Date: Thu, 15 Jan 2026 14:48:56 +0100 [thread overview]
Message-ID: <20260115-beautiful-ambitious-swine-c26a0d@quoll> (raw)
In-Reply-To: <20260114153337.46765-6-john.madieu.xa@bp.renesas.com>
On Wed, Jan 14, 2026 at 04:33:26PM +0100, John Madieu wrote:
> Extend the existing device tree bindings for Renesas RZ/G3S PCIe
> controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
> controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
> differences:
>
> - Uses a different device ID
> - Supports PCIe Gen3 (8.0 GT/s) link speeds
> - Uses a different clock naming (clkpmu vs clkl1pm)
> - Has a different set of interrupts, interrupt ordering, and reset signals
>
> Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
> .../bindings/pci/renesas,r9a08g045-pcie.yaml | 243 +++++++++++++-----
> 1 file changed, 172 insertions(+), 71 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> index d668782546a2..c68bc76af35d 100644
> --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> @@ -10,85 +10,34 @@ maintainers:
> - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> description:
> - Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
> - 4.0 and supports up to 5 GT/s (Gen2).
> + Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
> + Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
> + up to 8 GT/s (Gen3) for RZ/G3E.
>
> properties:
> compatible:
> - const: renesas,r9a08g045-pcie # RZ/G3S
> + enum:
> + - renesas,r9a08g045-pcie # RZ/G3S
> + - renesas,r9a09g047-pcie # RZ/G3E
>
> reg:
> maxItems: 1
>
> - interrupts:
> - items:
Same review as already in the past for Renesas. Broadest constraints
always stay here and list should share items.
> - - description: System error interrupt
> - - description: System error on correctable error interrupt
> - - description: System error on non-fatal error interrupt
> - - description: System error on fatal error interrupt
> - - description: AXI error interrupt
> - - description: INTA interrupt
> - - description: INTB interrupt
> - - description: INTC interrupt
> - - description: INTD interrupt
> - - description: MSI interrupt
> - - description: Link bandwidth interrupt
> - - description: PME interrupt
> - - description: DMA interrupt
> - - description: PCIe event interrupt
> - - description: Message interrupt
> - - description: All interrupts
> -
> - interrupt-names:
> - items:
> - - description: serr
> - - description: ser_cor
> - - description: serr_nonfatal
> - - description: serr_fatal
> - - description: axi_err
> - - description: inta
> - - description: intb
> - - description: intc
> - - description: intd
> - - description: msi
> - - description: link_bandwidth
> - - description: pm_pme
> - - description: dma
> - - description: pcie_evt
> - - description: msg
> - - description: all
> + interrupts: true
> +
> + interrupt-names: true
>
> interrupt-controller: true
>
> clocks:
> - items:
> - - description: System clock
> - - description: PM control clock
> + maxItems: 2
>
> clock-names:
> - items:
> - - description: aclk
> - - description: pm
> -
> - resets:
> - items:
> - - description: AXI2PCIe Bridge reset
> - - description: Data link layer/transaction layer reset
> - - description: Transaction layer (ACLK domain) reset
> - - description: Transaction layer (PCLK domain) reset
> - - description: Physical layer reset
> - - description: Configuration register reset
> - - description: Configuration register reset
> -
> - reset-names:
> - items:
> - - description: aresetn
> - - description: rst_b
> - - description: rst_gp_b
> - - description: rst_ps_b
> - - description: rst_rsm_b
> - - description: rst_cfg_b
> - - description: rst_load_b
> + maxItems: 2
> +
> + resets: true
> +
> + reset-names: true
>
> power-domains:
> maxItems: 1
> @@ -128,11 +77,12 @@ patternProperties:
> const: 0x1912
>
> device-id:
> - const: 0x0033
> + enum:
> + - 0x0033
> + - 0x0039
>
> clocks:
> - items:
> - - description: Reference clock
> + maxItems: 1
>
> clock-names:
> items:
> @@ -142,8 +92,6 @@ patternProperties:
> - device_type
> - vendor-id
> - device-id
> - - clocks
> - - clock-names
>
> unevaluatedProperties: false
>
> @@ -167,6 +115,159 @@ required:
>
> allOf:
> - $ref: /schemas/pci/pci-host-bridge.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a08g045-pcie
> + then:
> + properties:
> + interrupts:
> + items:
> + - description: System error interrupt
> + - description: System error on correctable error interrupt
> + - description: System error on non-fatal error interrupt
> + - description: System error on fatal error interrupt
> + - description: AXI error interrupt
> + - description: INTA interrupt
> + - description: INTB interrupt
> + - description: INTC interrupt
> + - description: INTD interrupt
> + - description: MSI interrupt
> + - description: Link bandwidth interrupt
> + - description: PME interrupt
> + - description: DMA interrupt
> + - description: PCIe event interrupt
> + - description: Message interrupt
> + - description: All interrupts
> + interrupt-names:
> + items:
> + - const: serr
So serr is first...
> + - const: serr_cor
> + - const: serr_nonfatal
> + - const: serr_fatal
> + - const: axi_err
> + - const: inta
> + - const: intb
> + - const: intc
> + - const: intd
> + - const: msi
> + - const: link_bandwidth
> + - const: pm_pme
> + - const: dma
> + - const: pcie_evt
> + - const: msg
> + - const: all
> + clocks:
> + items:
> + - description: System clock
> + - description: PM control clock
> + clock-names:
> + items:
> + - const: aclk
> + - const: pm
> + resets:
> + items:
> + - description: AXI2PCIe Bridge reset
> + - description: Data link layer/transaction layer reset
> + - description: Transaction layer (ACLK domain) reset
> + - description: Transaction layer (PCLK domain) reset
> + - description: Physical layer reset
> + - description: Configuration register reset
> + - description: Configuration register reset
> + reset-names:
> + items:
> + - const: aresetn
> + - const: rst_b
> + - const: rst_gp_b
> + - const: rst_ps_b
> + - const: rst_rsm_b
> + - const: rst_cfg_b
> + - const: rst_load_b
> + patternProperties:
> + "^pcie@0,[0-0]$":
> + properties:
> + device-id:
> + const: 0x0033
> + required:
> + - clocks
> + - clock-names
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g047-pcie
> + then:
> + properties:
> + interrupts:
> + items:
> + - description: All interrupts
> + - description: INTA interrupt
> + - description: INTB interrupt
> + - description: INTC interrupt
> + - description: INTD interrupt
> + - description: MSI interrupt
> + - description: Link bandwidth interrupt
> + - description: Link equalization request interrupt
> + - description: PME interrupt
> + - description: System error interrupt
> + - description: System error on correctable error interrupt
> + - description: System error on non-fatal error interrupt
> + - description: System error on fatal error interrupt
> + - description: DMA interrupt
> + - description: PCIe event interrupt
> + - description: AXI error interrupt
> + - description: Message interrupt
> + - description: Turn off event interrupt
> + - description: PMU power off interrupt
> + - description: D3 event function 0 interrupt
> + - description: D3 event function 1 interrupt
> + - description: Configuration PMCSR write clear function 0 interrupt
> + - description: Configuration PMCSR write clear function 1 interrupt
> + interrupt-names:
> + items:
> + - const: all
> + - const: inta
> + - const: intb
> + - const: intc
> + - const: intd
> + - const: msi
> + - const: link_bandwidth
> + - const: link_equalization_request
> + - const: pm_pme
> + - const: serr
And middle? What sort of mess is this?
Please learn from existing review, organize internal knowledge so we
won't be repeating the same.
I am not reviewing the rest.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-01-15 13:48 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-14 15:33 [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support John Madieu
2026-01-14 15:33 ` [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path John Madieu
2026-01-15 13:13 ` claudiu beznea
2026-01-16 21:00 ` John Madieu
2026-01-19 14:03 ` Claudiu Beznea
2026-01-20 20:11 ` John Madieu
2026-01-19 14:04 ` Claudiu Beznea
2026-01-20 20:05 ` John Madieu
2026-01-21 8:10 ` Biju Das
2026-01-14 15:33 ` [PATCH 02/16] PCI: rzg3s-host: Fix inbound window size tracking John Madieu
2026-01-19 14:06 ` Claudiu Beznea
2026-01-14 15:33 ` [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks John Madieu
2026-01-20 10:49 ` Geert Uytterhoeven
2026-01-20 19:08 ` John Madieu
2026-01-22 16:21 ` John Madieu
2026-01-22 16:29 ` Geert Uytterhoeven
2026-01-23 11:29 ` John Madieu
2026-01-23 11:39 ` Lad, Prabhakar
2026-01-23 12:32 ` John Madieu
2026-01-14 15:33 ` [PATCH 04/16] clk: renesas: r9a09g047: Add PCIe clocks and reset John Madieu
2026-01-20 11:03 ` Geert Uytterhoeven
2026-01-20 14:04 ` John Madieu
2026-01-14 15:33 ` [PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC John Madieu
2026-01-15 13:48 ` Krzysztof Kozlowski [this message]
2026-01-16 20:55 ` John Madieu
2026-01-15 13:55 ` claudiu beznea
2026-01-14 15:33 ` [PATCH 06/16] PCI: rzg3s-host: Make SYSC register offsets SoC-specific John Madieu
2026-01-19 18:14 ` Claudiu Beznea
2026-01-20 19:58 ` John Madieu
2026-01-14 15:33 ` [PATCH 07/16] PCI: rzg3s-host: Make configuration reset lines optional John Madieu
2026-01-14 22:38 ` Bjorn Helgaas
2026-01-15 9:44 ` John Madieu
2026-01-19 18:14 ` Claudiu Beznea
2026-01-14 15:33 ` [PATCH 08/16] PCI: rzg3s-host: Make inbound window setup SoC-specific John Madieu
2026-01-19 18:15 ` Claudiu Beznea
2026-01-20 19:52 ` John Madieu
2026-01-14 15:33 ` [PATCH 09/16] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks John Madieu
2026-01-14 22:40 ` Bjorn Helgaas
2026-01-15 9:43 ` John Madieu
2026-01-19 18:21 ` Claudiu Beznea
2026-01-14 15:33 ` [PATCH 10/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility John Madieu
2026-01-15 13:49 ` kernel test robot
2026-01-14 15:33 ` [PATCH 11/16] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support John Madieu
2026-01-19 18:21 ` Claudiu Beznea
2026-01-14 15:33 ` [PATCH 12/16] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller John Madieu
2026-01-19 18:25 ` Claudiu Beznea
2026-01-14 15:33 ` [PATCH 13/16] arm64: dts: renesas: r9a09g047: Add PCIe node John Madieu
2026-01-14 15:33 ` [PATCH 14/16] arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock John Madieu
2026-01-14 15:33 ` [PATCH 15/16] arm64: dts: renesas: r9a09g047e57-smarc: Add PCIe pincontrol John Madieu
2026-01-14 15:33 ` [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe John Madieu
2026-01-14 16:19 ` Biju Das
2026-01-14 16:34 ` John Madieu
2026-01-14 16:50 ` Biju Das
2026-01-21 10:25 ` Geert Uytterhoeven
2026-01-21 10:27 ` John Madieu
2026-01-14 17:47 ` [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support Biju Das
2026-01-15 9:45 ` John Madieu
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