Re: [PATCH 10/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility

[kernel test robot <lkp@intel.com>]

Hi John,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20260114]
[cannot apply to pci/next pci/for-linus geert-renesas-devel/next geert-renesas-drivers/renesas-clk linus/master v6.19-rc5 v6.19-rc4 v6.19-rc3 v6.19-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/John-Madieu/PCI-rzg3s-host-Fix-reset-handling-in-probe-error-path/20260114-234634
base:   next-20260114
patch link:    https://lore.kernel.org/r/20260114153337.46765-11-john.madieu.xa%40bp.renesas.com
patch subject: [PATCH 10/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
config: powerpc64-randconfig-002-20260115 (https://download.01.org/0day-ci/archive/20260115/202601152104.pV9uMS76-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260115/202601152104.pV9uMS76-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601152104.pV9uMS76-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/pcie-rzg3s-host.c:1090:11: warning: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((mask), char: (unsigned char)0, unsigned char: (unsigned char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long long: (unsigned long long)0, long long: (unsigned long long)0, default: (mask)))' (aka 'unsigned int') is always false [-Wtautological-constant-out-of-range-compare]
    1090 |                                FIELD_PREP(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));
         |                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:137:3: note: expanded from macro 'FIELD_PREP'
     137 |                 __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: ");      \
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:79:50: note: expanded from macro '__BF_FIELD_CHECK_REG'
      79 |         BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) >               \
         |         ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~
      80 |                          __bf_cast_unsigned(reg, ~0ull),                \
         |                          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      81 |                          pfx "type of reg too small for mask")
         |                          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:58: note: expanded from macro 'BUILD_BUG_ON_MSG'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~
   include/linux/compiler_types.h:667:22: note: expanded from macro 'compiletime_assert'
     667 |         _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |         ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler_types.h:655:23: note: expanded from macro '_compiletime_assert'
     655 |         __compiletime_assert(condition, msg, prefix, suffix)
         |         ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler_types.h:647:9: note: expanded from macro '__compiletime_assert'
     647 |                 if (!(condition))                                       \
         |                       ^~~~~~~~~
   1 warning generated.


vim +1090 drivers/pci/controller/pcie-rzg3s-host.c

  1057	
  1058	static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
  1059	{
  1060		struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
  1061		u32 mask = GENMASK(31, 8);
  1062		struct resource_entry *ft;
  1063		struct resource *bus;
  1064		u8 subordinate_bus;
  1065		u8 secondary_bus;
  1066		u8 primary_bus;
  1067	
  1068		ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
  1069		if (!ft)
  1070			return -ENODEV;
  1071	
  1072		bus = ft->res;
  1073		primary_bus = bus->start;
  1074		secondary_bus = bus->start + 1;
  1075		subordinate_bus = bus->end;
  1076	
  1077		/* Enable access control to the CFGU */
  1078		writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
  1079			       host->axi + RZG3S_PCI_PERM);
  1080	
  1081		/* HW manual recommends to write 0xffffffff on initialization */
  1082		writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
  1083		writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
  1084	
  1085		/*
  1086		 * Explicitly program class code. RZ/G3E requires this configuration.
  1087		 * Harmless for RZ/G3S where this matches the hardware default.
  1088		 */
  1089		rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask,
> 1090				       FIELD_PREP(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));
  1091	
  1092		/* Disable access control to the CFGU */
  1093		writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
  1094	
  1095		/* Update bus info */
  1096		writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
  1097		writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
  1098		writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
  1099	
  1100		return 0;
  1101	}
  1102	

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