[PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support

[PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support

[John Madieu]

The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.

Key differences between RZ/G3E and RZ/G3S PCIe controllers:

Link Speed Support:
 - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s)
 - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only

Reset Control:
 - RZ/G3E: Uses register-based reset control mechanism
 - RZ/G3S: Uses exclusively external reset control signals

Inbound Window Configuration:
 - RZ/G3E: Requires precise power-of-2 window coverage with strict address
   alignment constraints. Non-power-of-2 memory regions must be split into
   multiple windows to avoid over-mapping, ensuring proper hardware address
   decoding for DMA operations.
 - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-2,
   creating single larger windows. The hardware tolerates over-mapped regions.

Class/Revision IDs:
 - RZ/G3E: Requires explicit setting of class/revision values
 - RZ/G3S: Has default values in hardware

Clock Naming:
 - RZ/G3E: Uses "clkpmu" PM control clock while CLKREQ_B is deasserting
 - RZ/G3S: Uses "clkl1pm" clock for power management

Phy Settings:
 - RZ/G3E: Does not need PHY settings as it works with default hw values
 - RZ/G3S: Requires explicit PHY settings

This series extends the existing driver to detect the SoC type from the device
tree compatible string and configure the controller appropriately. The updates
are minimal and focused on the hardware-specific differences while keeping the
common code paths unified.

Note: The clks "PCIE_0_REFCLK_IN" and "PCIE_0_CORECLKIN" are added by mistake in
hardware manual

John Madieu (16):
  PCI: rzg3s-host: Fix reset handling in probe error path
  PCI: rzg3s-host: Fix inbound window size tracking
  clk: renesas: rzv2h-cpg: Add support for init_off clocks
  clk: renesas: r9a09g047: Add PCIe clocks and reset
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
  PCI: rzg3s-host: Make SYSC register offsets SoC-specific
  PCI: rzg3s-host: Make configuration reset lines optional
  PCI: rzg3s-host: Make inbound window setup SoC-specific
  PCI: rzg3s-host: Add SoC-specific configuration and initialization
    callbacks
  PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
  PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
  PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
  arm64: dts: renesas: r9a09g047: Add PCIe node
  arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
  arm64: dts: renesas: r9a09g047e57-smarc: Add PCIe pincontrol
  arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

 .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243 +++++++----
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  68 +++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  11 +
 .../boot/dts/renesas/renesas-smarc2.dtsi      |   7 +
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  11 +
 drivers/clk/renesas/r9a09g047-cpg.c           |   5 +
 drivers/clk/renesas/rzv2h-cpg.c               |   9 +
 drivers/clk/renesas/rzv2h-cpg.h               |  18 +-
 drivers/pci/controller/pcie-rzg3s-host.c      | 393 +++++++++++++++---
 9 files changed, 632 insertions(+), 133 deletions(-)

-- 
2.25.1

[PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[John Madieu]

Fix incorrect reset_control_bulk_deassert() call in the probe error
path. When unwinding from a failed pci_host_probe(), the configuration
resets should be asserted to restore the hardware to its initial state,
not deasserted again.

Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver")
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 5aa58638903f..c1053f95bc95 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 
 host_probe_teardown:
 	rzg3s_pcie_teardown_irqdomain(host);
-	reset_control_bulk_deassert(host->data->num_cfg_resets,
+	reset_control_bulk_assert(host->data->num_cfg_resets,
 				    host->cfg_resets);
 rpm_put:
 	pm_runtime_put_sync(dev);
-- 
2.25.1

[PATCH 02/16] PCI: rzg3s-host: Fix inbound window size tracking

[John Madieu]

The current implementation incorrectly resets size_id each iteration
instead of accumulating, causing incorrect remaining size calculations
when mapping DMA regions across multiple windows.

Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver")
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index c1053f95bc95..205b60421be1 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -1313,7 +1313,7 @@ static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,
 
 		pci_addr += size;
 		cpu_addr += size;
-		size_id = size;
+		size_id += size;
 		id++;
 	}
 	*index = id;
-- 
2.25.1

[PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[John Madieu]

Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.

Add new macros DEF_MOD_INIT_OFF() to declare module clocks that should be
turned off during CPG probe if found in the opposite state.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c |  9 +++++++++
 drivers/clk/renesas/rzv2h-cpg.h | 18 ++++++++++++------
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 3f6299b9fec0..91bc54aec328 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1337,6 +1337,15 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
 		spin_unlock_irqrestore(&priv->rmw_lock, flags);
 	}
 
+	/*
+	 * Turn off clocks marked with init_off flag if they were left
+	 * enabled by the bootloader. This ensures a known initial state.
+	 */
+	if (mod->init_off && rzv2h_mod_clock_is_enabled(&clock->hw)) {
+		dev_dbg(dev, "Disabling clock %s (init_off)\n", mod->name);
+		rzv2h_mod_clock_endisable(&clock->hw, false);
+	}
+
 	return;
 
 fail:
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index dc957bdaf5e9..248e954c4075 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -250,6 +250,7 @@ enum clk_types {
  * @parent: id of parent clock
  * @critical: flag to indicate the clock is critical
  * @no_pm: flag to indicate PM is not supported
+ * @init_off: flag to indicate the clock should be turned off during probe
  * @on_index: control register index
  * @on_bit: ON bit
  * @mon_index: monitor register index
@@ -262,6 +263,7 @@ struct rzv2h_mod_clk {
 	u16 parent;
 	bool critical;
 	bool no_pm;
+	bool init_off;
 	u8 on_index;
 	u8 on_bit;
 	s8 mon_index;
@@ -269,14 +271,15 @@ struct rzv2h_mod_clk {
 	s8 ext_clk_mux_index;
 };
 
-#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
-		     _onbit, _monindex, _monbit, _ext_clk_mux_index) \
+#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _init_off, \
+		     _onindex, _onbit, _monindex, _monbit, _ext_clk_mux_index) \
 	{ \
 		.name = (_name), \
 		.mstop_data = (_mstop), \
 		.parent = (_parent), \
 		.critical = (_critical), \
 		.no_pm = (_no_pm), \
+		.init_off = (_init_off), \
 		.on_index = (_onindex), \
 		.on_bit = (_onbit), \
 		.mon_index = (_monindex), \
@@ -285,17 +288,20 @@ struct rzv2h_mod_clk {
 	}
 
 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, false, _onindex, _onbit, _monindex, _monbit, -1)
 
 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, true, false, false, _onindex, _onbit, _monindex, _monbit, -1)
+
+#define DEF_MOD_INIT_OFF(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, true, _onindex, _onbit, _monindex, _monbit, -1)
 
 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, true, false, _onindex, _onbit, _monindex, _monbit, -1)
 
 #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
 			     _ext_clk_mux_index) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, false, _onindex, _onbit, _monindex, _monbit, \
 		     _ext_clk_mux_index)
 
 /**
-- 
2.25.1

[PATCH 04/16] clk: renesas: r9a09g047: Add PCIe clocks and reset

[John Madieu]

Add necessary clocks and reset entries for the PCIe controller

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 1e9896742a06..01a7a5fcfe9e 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -438,6 +438,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(3, BIT(4))),
 	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
 						BUS_MSTOP(2, BIT(15))),
+	DEF_MOD_INIT_OFF("pcie_aclk",		CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
+						BUS_MSTOP(1, BIT(15))),
+	DEF_MOD_INIT_OFF("pcie_clk_pmu",	CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
+						BUS_MSTOP(1, BIT(15))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -503,6 +507,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */
 	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */
 	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */
+	DEF_RST(11, 2, 5, 3),		/* PCIE_ARESETN */
 	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
 	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
 	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
-- 
2.25.1

[PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC

[John Madieu]

Extend the existing device tree bindings for Renesas RZ/G3S PCIe
controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
differences:

 - Uses a different device ID
 - Supports PCIe Gen3 (8.0 GT/s) link speeds
 - Uses a different clock naming (clkpmu vs clkl1pm)
 - Has a different set of interrupts, interrupt ordering, and reset signals

Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243 +++++++++++++-----
 1 file changed, 172 insertions(+), 71 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
index d668782546a2..c68bc76af35d 100644
--- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
@@ -10,85 +10,34 @@ maintainers:
   - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
 
 description:
-  Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
-  4.0 and supports up to 5 GT/s (Gen2).
+  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
+  Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
+  up to 8 GT/s (Gen3) for RZ/G3E.
 
 properties:
   compatible:
-    const: renesas,r9a08g045-pcie # RZ/G3S
+    enum:
+      - renesas,r9a08g045-pcie # RZ/G3S
+      - renesas,r9a09g047-pcie # RZ/G3E
 
   reg:
     maxItems: 1
 
-  interrupts:
-    items:
-      - description: System error interrupt
-      - description: System error on correctable error interrupt
-      - description: System error on non-fatal error interrupt
-      - description: System error on fatal error interrupt
-      - description: AXI error interrupt
-      - description: INTA interrupt
-      - description: INTB interrupt
-      - description: INTC interrupt
-      - description: INTD interrupt
-      - description: MSI interrupt
-      - description: Link bandwidth interrupt
-      - description: PME interrupt
-      - description: DMA interrupt
-      - description: PCIe event interrupt
-      - description: Message interrupt
-      - description: All interrupts
-
-  interrupt-names:
-    items:
-      - description: serr
-      - description: ser_cor
-      - description: serr_nonfatal
-      - description: serr_fatal
-      - description: axi_err
-      - description: inta
-      - description: intb
-      - description: intc
-      - description: intd
-      - description: msi
-      - description: link_bandwidth
-      - description: pm_pme
-      - description: dma
-      - description: pcie_evt
-      - description: msg
-      - description: all
+  interrupts: true
+
+  interrupt-names: true
 
   interrupt-controller: true
 
   clocks:
-    items:
-      - description: System clock
-      - description: PM control clock
+    maxItems: 2
 
   clock-names:
-    items:
-      - description: aclk
-      - description: pm
-
-  resets:
-    items:
-      - description: AXI2PCIe Bridge reset
-      - description: Data link layer/transaction layer reset
-      - description: Transaction layer (ACLK domain) reset
-      - description: Transaction layer (PCLK domain) reset
-      - description: Physical layer reset
-      - description: Configuration register reset
-      - description: Configuration register reset
-
-  reset-names:
-    items:
-      - description: aresetn
-      - description: rst_b
-      - description: rst_gp_b
-      - description: rst_ps_b
-      - description: rst_rsm_b
-      - description: rst_cfg_b
-      - description: rst_load_b
+    maxItems: 2
+
+  resets: true
+
+  reset-names: true
 
   power-domains:
     maxItems: 1
@@ -128,11 +77,12 @@ patternProperties:
         const: 0x1912
 
       device-id:
-        const: 0x0033
+        enum:
+          - 0x0033
+          - 0x0039
 
       clocks:
-        items:
-          - description: Reference clock
+        maxItems: 1
 
       clock-names:
         items:
@@ -142,8 +92,6 @@ patternProperties:
       - device_type
       - vendor-id
       - device-id
-      - clocks
-      - clock-names
 
     unevaluatedProperties: false
 
@@ -167,6 +115,159 @@ required:
 
 allOf:
   - $ref: /schemas/pci/pci-host-bridge.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g045-pcie
+    then:
+      properties:
+        interrupts:
+          items:
+            - description: System error interrupt
+            - description: System error on correctable error interrupt
+            - description: System error on non-fatal error interrupt
+            - description: System error on fatal error interrupt
+            - description: AXI error interrupt
+            - description: INTA interrupt
+            - description: INTB interrupt
+            - description: INTC interrupt
+            - description: INTD interrupt
+            - description: MSI interrupt
+            - description: Link bandwidth interrupt
+            - description: PME interrupt
+            - description: DMA interrupt
+            - description: PCIe event interrupt
+            - description: Message interrupt
+            - description: All interrupts
+        interrupt-names:
+          items:
+            - const: serr
+            - const: serr_cor
+            - const: serr_nonfatal
+            - const: serr_fatal
+            - const: axi_err
+            - const: inta
+            - const: intb
+            - const: intc
+            - const: intd
+            - const: msi
+            - const: link_bandwidth
+            - const: pm_pme
+            - const: dma
+            - const: pcie_evt
+            - const: msg
+            - const: all
+        clocks:
+          items:
+            - description: System clock
+            - description: PM control clock
+        clock-names:
+          items:
+            - const: aclk
+            - const: pm
+        resets:
+          items:
+            - description: AXI2PCIe Bridge reset
+            - description: Data link layer/transaction layer reset
+            - description: Transaction layer (ACLK domain) reset
+            - description: Transaction layer (PCLK domain) reset
+            - description: Physical layer reset
+            - description: Configuration register reset
+            - description: Configuration register reset
+        reset-names:
+          items:
+            - const: aresetn
+            - const: rst_b
+            - const: rst_gp_b
+            - const: rst_ps_b
+            - const: rst_rsm_b
+            - const: rst_cfg_b
+            - const: rst_load_b
+      patternProperties:
+        "^pcie@0,[0-0]$":
+          properties:
+            device-id:
+              const: 0x0033
+          required:
+            - clocks
+            - clock-names
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g047-pcie
+    then:
+      properties:
+        interrupts:
+          items:
+            - description: All interrupts
+            - description: INTA interrupt
+            - description: INTB interrupt
+            - description: INTC interrupt
+            - description: INTD interrupt
+            - description: MSI interrupt
+            - description: Link bandwidth interrupt
+            - description: Link equalization request interrupt
+            - description: PME interrupt
+            - description: System error interrupt
+            - description: System error on correctable error interrupt
+            - description: System error on non-fatal error interrupt
+            - description: System error on fatal error interrupt
+            - description: DMA interrupt
+            - description: PCIe event interrupt
+            - description: AXI error interrupt
+            - description: Message interrupt
+            - description: Turn off event interrupt
+            - description: PMU power off interrupt
+            - description: D3 event function 0 interrupt
+            - description: D3 event function 1 interrupt
+            - description: Configuration PMCSR write clear function 0 interrupt
+            - description: Configuration PMCSR write clear function 1 interrupt
+        interrupt-names:
+          items:
+            - const: all
+            - const: inta
+            - const: intb
+            - const: intc
+            - const: intd
+            - const: msi
+            - const: link_bandwidth
+            - const: link_equalization_request
+            - const: pm_pme
+            - const: serr
+            - const: serr_cor
+            - const: serr_nonfatal
+            - const: serr_fatal
+            - const: dma
+            - const: pcie_evt
+            - const: axi_err
+            - const: msg
+            - const: turn_off_event
+            - const: pmu_poweroff
+            - const: d3_event_f0
+            - const: d3_event_f1
+            - const: cfg_pmcsr_writeclear_f0
+            - const: cfg_pmcsr_writeclear_f1
+        clocks:
+          items:
+            - description: System clock
+            - description: PMU clock
+        clock-names:
+          items:
+            - const: aclk
+            - const: pmu
+        resets:
+          items:
+            - description: AXI2PCIe Bridge reset
+        reset-names:
+          items:
+            - const: aresetn
+      patternProperties:
+        "^pcie@0,[0-0]$":
+          properties:
+            device-id:
+              const: 0x0039
 
 unevaluatedProperties: false
 
-- 
2.25.1

[PATCH 06/16] PCI: rzg3s-host: Make SYSC register offsets SoC-specific

[John Madieu]

In preparation for adding RZ/G3E support, move the RST_RSM_B register
offset and mask into a SoC-specific data structure. Compared with RZ/G3S,
the RZ/G3E SYSC controls different functionalities for the PCIe controller.

Make SYSC operations conditional on the presence of register offset
information, allowing the driver to handle SoCs that don't use the
RST_RSM_B signal.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 93 +++++++++++++++++-------
 1 file changed, 67 insertions(+), 26 deletions(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 205b60421be1..44728771afa3 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -159,10 +159,6 @@
 
 #define RZG3S_PCI_CFG_PCIEC			0x60
 
-/* System controller registers */
-#define RZG3S_SYS_PCIE_RST_RSM_B		0xd74
-#define RZG3S_SYS_PCIE_RST_RSM_B_MASK		BIT(0)
-
 /* Maximum number of windows */
 #define RZG3S_MAX_WINDOWS			8
 
@@ -174,6 +170,34 @@
 /* Timeouts experimentally determined */
 #define RZG3S_REQ_ISSUE_TIMEOUT_US		2500
 
+/**
+ * struct rzg3s_sysc_function - System Controller register function descriptor
+ * @offset: Register offset from the System Controller base address
+ * @mask: Bit mask for the function within the register
+ */
+struct rzg3s_sysc_function {
+	u32 offset;
+	u32 mask;
+};
+
+/**
+ * struct rzg3s_sysc_info - RZ/G3S System Controller function info
+ * @rst_rsm_b: Reset RSM_B function descriptor
+ */
+struct rzg3s_sysc_info {
+	struct rzg3s_sysc_function rst_rsm_b;
+};
+
+/**
+ * struct rzg3s_sysc - RZ/G3S System Controller descriptor
+ * @regmap: System controller regmap
+ * @info: System controller info
+ */
+struct rzg3s_sysc {
+	struct regmap *regmap;
+	const struct rzg3s_sysc_info *info;
+};
+
 /**
  * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
  * @domain: IRQ domain
@@ -203,6 +227,7 @@ struct rzg3s_pcie_host;
  *                power-on
  * @cfg_resets: array with the resets that need to be de-asserted after
  *              configuration
+ * @sysc_info: SYSC functionalities
  * @num_power_resets: number of power resets
  * @num_cfg_resets: number of configuration resets
  */
@@ -210,6 +235,7 @@ struct rzg3s_pcie_soc_data {
 	int (*init_phy)(struct rzg3s_pcie_host *host);
 	const char * const *power_resets;
 	const char * const *cfg_resets;
+	struct rzg3s_sysc_info sysc_info;
 	u8 num_power_resets;
 	u8 num_cfg_resets;
 };
@@ -233,7 +259,7 @@ struct rzg3s_pcie_port {
  * @dev: struct device
  * @power_resets: reset control signals that should be set after power up
  * @cfg_resets: reset control signals that should be set after configuration
- * @sysc: SYSC regmap
+ * @sysc: SYSC descriptor
  * @intx_domain: INTx IRQ domain
  * @data: SoC specific data
  * @msi: MSI data structure
@@ -248,7 +274,7 @@ struct rzg3s_pcie_host {
 	struct device *dev;
 	struct reset_control_bulk_data *power_resets;
 	struct reset_control_bulk_data *cfg_resets;
-	struct regmap *sysc;
+	struct rzg3s_sysc *sysc;
 	struct irq_domain *intx_domain;
 	const struct rzg3s_pcie_soc_data *data;
 	struct rzg3s_pcie_msi msi;
@@ -1516,6 +1542,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	struct device_node *sysc_np __free(device_node) =
 		of_parse_phandle(np, "renesas,sysc", 0);
 	struct rzg3s_pcie_host *host;
+	struct rzg3s_sysc *sysc;
 	int ret;
 
 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
@@ -1527,6 +1554,13 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	host->data = device_get_match_data(dev);
 	platform_set_drvdata(pdev, host);
 
+	host->sysc = devm_kzalloc(dev, sizeof(*host->sysc), GFP_KERNEL);
+	if (!host->sysc)
+		return -ENOMEM;
+
+	sysc = host->sysc;
+	sysc->info = &host->data->sysc_info;
+
 	host->axi = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(host->axi))
 		return PTR_ERR(host->axi);
@@ -1540,15 +1574,16 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	host->sysc = syscon_node_to_regmap(sysc_np);
-	if (IS_ERR(host->sysc)) {
-		ret = PTR_ERR(host->sysc);
+	sysc->regmap = syscon_node_to_regmap(sysc_np);
+	if (IS_ERR(sysc->regmap)) {
+		ret = PTR_ERR(sysc->regmap);
 		goto port_refclk_put;
 	}
 
-	ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
-				 RZG3S_SYS_PCIE_RST_RSM_B_MASK,
-				 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
+	ret = regmap_update_bits(sysc->regmap,
+				 sysc->info->rst_rsm_b.offset,
+				 sysc->info->rst_rsm_b.mask,
+				 field_prep(sysc->info->rst_rsm_b.mask, 1));
 	if (ret)
 		goto port_refclk_put;
 
@@ -1601,9 +1636,9 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	 * SYSC RST_RSM_B signal need to be asserted before turning off the
 	 * power to the PHY.
 	 */
-	regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
-			   RZG3S_SYS_PCIE_RST_RSM_B_MASK,
-			   FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
+	regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
+			   sysc->info->rst_rsm_b.mask,
+			   field_prep(sysc->info->rst_rsm_b.mask, 0));
 port_refclk_put:
 	clk_put(host->port.refclk);
 
@@ -1615,7 +1650,7 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
 	struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
 	const struct rzg3s_pcie_soc_data *data = host->data;
 	struct rzg3s_pcie_port *port = &host->port;
-	struct regmap *sysc = host->sysc;
+	struct rzg3s_sysc *sysc = host->sysc;
 	int ret;
 
 	ret = pm_runtime_put_sync(dev);
@@ -1634,9 +1669,9 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
 	if (ret)
 		goto power_resets_restore;
 
-	ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
-				 RZG3S_SYS_PCIE_RST_RSM_B_MASK,
-				 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
+	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
+				 sysc->info->rst_rsm_b.mask,
+				 field_prep(sysc->info->rst_rsm_b.mask, 0));
 	if (ret)
 		goto cfg_resets_restore;
 
@@ -1659,12 +1694,12 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)
 {
 	struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
 	const struct rzg3s_pcie_soc_data *data = host->data;
-	struct regmap *sysc = host->sysc;
+	struct rzg3s_sysc *sysc = host->sysc;
 	int ret;
 
-	ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
-				 RZG3S_SYS_PCIE_RST_RSM_B_MASK,
-				 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
+	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
+				 sysc->info->rst_rsm_b.mask,
+				 field_prep(sysc->info->rst_rsm_b.mask, 1));
 	if (ret)
 		return ret;
 
@@ -1693,9 +1728,9 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)
 	reset_control_bulk_assert(data->num_power_resets,
 				  host->power_resets);
 assert_rst_rsm_b:
-	regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
-			   RZG3S_SYS_PCIE_RST_RSM_B_MASK,
-			   FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
+	regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
+			   sysc->info->rst_rsm_b.mask,
+			   field_prep(sysc->info->rst_rsm_b.mask, 0));
 	return ret;
 }
 
@@ -1718,6 +1753,12 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
 	.cfg_resets = rzg3s_soc_cfg_resets,
 	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
 	.init_phy = rzg3s_soc_pcie_init_phy,
+	.sysc_info = {
+		.rst_rsm_b = {
+			.offset = 0xd74,
+			.mask = BIT(0),
+		},
+	},
 };
 
 static const struct of_device_id rzg3s_pcie_of_match[] = {
-- 
2.25.1

[PATCH 07/16] PCI: rzg3s-host: Make configuration reset lines optional

[John Madieu]

Some SoC variants such as RZ/G3E handles configuration reset control
through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets
optional by using devm_reset_control_bulk_get_optional_exclusive() to allow
SoCs to use alternative or complementaty reset control mechanisms.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 44728771afa3..fcedccadecf6 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -1161,9 +1161,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)
 	if (ret)
 		return ret;
 
-	return devm_reset_control_bulk_get_exclusive(host->dev,
-						     data->num_cfg_resets,
-						     host->cfg_resets);
+	return devm_reset_control_bulk_get_optional_exclusive(host->dev,
+							      data->num_cfg_resets,
+							      host->cfg_resets);
 }
 
 static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)
-- 
2.25.1

[PATCH 08/16] PCI: rzg3s-host: Make inbound window setup SoC-specific

[John Madieu]

Different RZ/G3 SoCs have different requirements for inbound window
configuration. While both require power-of-2 sized windows (4KB * 2^N),
they differ in how non-power-of-2 memory regions are handled:

- RZ/G3S: Uses roundup_pow_of_two() to create a single larger window
  that may over-map beyond the actual memory region. This approach is
  simpler but relies on hardware tolerance for over-mapped regions.

- RZ/G3E: Requires precise coverage without over-mapping. Memory regions
  must be split into multiple power-of-2 windows, and window sizes must
  respect address alignment constraints to ensure proper hardware address
  decoding.

Move the inbound window sizing and splitting logic to a SoC-specific
callback to accommodate these differences. This allows each SoC variant
to implement its own window setup strategy while maintaining the common
window programming sequence.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index fcedccadecf6..a9773e5f25c7 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -223,6 +223,7 @@ struct rzg3s_pcie_host;
 /**
  * struct rzg3s_pcie_soc_data - SoC specific data
  * @init_phy: PHY initialization function
+ * @set_inbound_windows: SoC-specific function to set up inbound windows
  * @power_resets: array with the resets that need to be de-asserted after
  *                power-on
  * @cfg_resets: array with the resets that need to be de-asserted after
@@ -233,6 +234,9 @@ struct rzg3s_pcie_host;
  */
 struct rzg3s_pcie_soc_data {
 	int (*init_phy)(struct rzg3s_pcie_host *host);
+	int (*set_inbound_windows)(struct rzg3s_pcie_host *host,
+				   struct resource_entry *entry,
+				   int *index);
 	const char * const *power_resets;
 	const char * const *cfg_resets;
 	struct rzg3s_sysc_info sysc_info;
@@ -1354,7 +1358,7 @@ static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host)
 	int i = 0, ret;
 
 	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
-		ret = rzg3s_pcie_set_inbound_windows(host, entry, &i);
+		ret = host->data->set_inbound_windows(host, entry, &i);
 		if (ret)
 			return ret;
 	}
@@ -1753,6 +1757,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
 	.cfg_resets = rzg3s_soc_cfg_resets,
 	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
 	.init_phy = rzg3s_soc_pcie_init_phy,
+	.set_inbound_windows = rzg3s_pcie_set_inbound_windows,
 	.sysc_info = {
 		.rst_rsm_b = {
 			.offset = 0xd74,
-- 
2.25.1

[PATCH 09/16] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks

[John Madieu]

Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks
to handle SoC-specific configuration methods. While RZ/G3S uses the Linux
reset framework with dedicated reset lines, other SoC variants like RZ/G3E
control configuration resets through PCIe AXI registers.

As Linux reset bulk API gracefully handles optional NULL reset lines
(num_cfg_resets = 0 for RZ/G3E), the driver continues to use the standard
reset framework when reset lines are available, while custom callbacks
are only invoked when provided.

This provides a balanced pattern where:
- RZ/G3S: Uses reset framework only, no callbacks needed
- RZ/G3E: Sets num_cfg_resets=0, provides cfg_pre_init/cfg_post_init/cfg_deinit
- In addition to that, RZ/G3E requires explicit cfg reset and clok turned off
  to put the PCIe IP in a known state.

Add cfg_pre_init, cfg_post_init, and cfg_deinit callbacks to support
custom configuration mechanism in preparation to RZ/G3E PCIe support.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 54 ++++++++++++++++++------
 1 file changed, 40 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index a9773e5f25c7..bb071bacd0b2 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -224,6 +224,9 @@ struct rzg3s_pcie_host;
  * struct rzg3s_pcie_soc_data - SoC specific data
  * @init_phy: PHY initialization function
  * @set_inbound_windows: SoC-specific function to set up inbound windows
+ * @cfg_pre_init: Optional callback for SoC-specific pre-configuration
+ * @cfg_post_init: Optional callback for SoC-specific post-configuration
+ * @cfg_deinit: Optional callback for SoC-specific de-initialization
  * @power_resets: array with the resets that need to be de-asserted after
  *                power-on
  * @cfg_resets: array with the resets that need to be de-asserted after
@@ -237,6 +240,9 @@ struct rzg3s_pcie_soc_data {
 	int (*set_inbound_windows)(struct rzg3s_pcie_host *host,
 				   struct resource_entry *entry,
 				   int *index);
+	void (*cfg_pre_init)(struct rzg3s_pcie_host *host);
+	int (*cfg_post_init)(struct rzg3s_pcie_host *host);
+	void (*cfg_deinit)(struct rzg3s_pcie_host *host);
 	const char * const *power_resets;
 	const char * const *cfg_resets;
 	struct rzg3s_sysc_info sysc_info;
@@ -1119,6 +1125,12 @@ static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host)
 	writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS);
 }
 
+static int rzg3s_cfg_post_init(struct rzg3s_pcie_host *host)
+{
+	return reset_control_bulk_deassert(host->data->num_cfg_resets,
+					   host->cfg_resets);
+}
+
 static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host)
 {
 	const struct rzg3s_pcie_soc_data *data = host->data;
@@ -1233,6 +1245,10 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
 	u32 val;
 	int ret;
 
+	/* SoC-specific pre-configuration */
+	if (host->data->cfg_pre_init)
+		host->data->cfg_pre_init(host);
+
 	/* Initialize the PCIe related registers */
 	ret = rzg3s_pcie_config_init(host);
 	if (ret)
@@ -1245,8 +1261,8 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
 	/* Initialize the interrupts */
 	rzg3s_pcie_irq_init(host);
 
-	ret = reset_control_bulk_deassert(host->data->num_cfg_resets,
-					  host->cfg_resets);
+	/* SoC-specific post-configuration */
+	ret = host->data->cfg_post_init(host);
 	if (ret)
 		goto disable_port_refclk;
 
@@ -1257,14 +1273,17 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
 				 PCIE_LINK_WAIT_SLEEP_MS * MILLI *
 				 PCIE_LINK_WAIT_MAX_RETRIES);
 	if (ret)
-		goto cfg_resets_deassert;
+		goto cfg_deinit;
 
 	val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
 	dev_info(host->dev, "PCIe link status [0x%x]\n", val);
 
 	return 0;
 
-cfg_resets_deassert:
+cfg_deinit:
+	if (host->data->cfg_deinit)
+		host->data->cfg_deinit(host);
+
 	reset_control_bulk_assert(host->data->num_cfg_resets,
 				  host->cfg_resets);
 disable_port_refclk:
@@ -1609,6 +1628,9 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto rpm_disable;
 
+	if (host->data->cfg_deinit)
+		host->data->cfg_deinit(host);
+
 	raw_spin_lock_init(&host->hw_lock);
 
 	ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain,
@@ -1663,32 +1685,35 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
 
 	clk_disable_unprepare(port->refclk);
 
-	ret = reset_control_bulk_assert(data->num_power_resets,
-					host->power_resets);
-	if (ret)
-		goto refclk_restore;
+	/* SoC-specific de-initialization */
+	if (data->cfg_deinit)
+		data->cfg_deinit(host);
 
 	ret = reset_control_bulk_assert(data->num_cfg_resets,
 					host->cfg_resets);
 	if (ret)
-		goto power_resets_restore;
+		goto cfg_reinit;
+
+	ret = reset_control_bulk_assert(data->num_power_resets,
+					host->power_resets);
+	if (ret)
+		goto cfg_reinit;
 
 	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
 				 sysc->info->rst_rsm_b.mask,
 				 field_prep(sysc->info->rst_rsm_b.mask, 0));
 	if (ret)
-		goto cfg_resets_restore;
+		goto power_resets_restore;
 
 	return 0;
 
 	/* Restore the previous state if any error happens */
-cfg_resets_restore:
-	reset_control_bulk_deassert(data->num_cfg_resets,
-				    host->cfg_resets);
 power_resets_restore:
 	reset_control_bulk_deassert(data->num_power_resets,
 				    host->power_resets);
-refclk_restore:
+cfg_reinit:
+	data->cfg_post_init(host);
+
 	clk_prepare_enable(port->refclk);
 	pm_runtime_resume_and_get(dev);
 	return ret;
@@ -1756,6 +1781,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
 	.num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets),
 	.cfg_resets = rzg3s_soc_cfg_resets,
 	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
+	.cfg_post_init = rzg3s_cfg_post_init,
 	.init_phy = rzg3s_soc_pcie_init_phy,
 	.set_inbound_windows = rzg3s_pcie_set_inbound_windows,
 	.sysc_info = {
-- 
2.25.1

[PATCH 10/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility

[John Madieu]

Program the class code register explicitly during PCIe configuration
initialization. RZ/G3E requires this register to be set, while RZ/G3S
has these values as hardware defaults.

This configuration is harmless for RZ/G3S where these match the hardware
defaults, and necessary for RZ/G3E to properly identify the device as a
PCI bridge.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index bb071bacd0b2..18fccc687c6b 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -1058,6 +1058,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)
 static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
 {
 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
+	u32 mask = GENMASK(31, 8);
 	struct resource_entry *ft;
 	struct resource *bus;
 	u8 subordinate_bus;
@@ -1081,6 +1082,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
 	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
 	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
 
+	/*
+	 * Explicitly program class code. RZ/G3E requires this configuration.
+	 * Harmless for RZ/G3S where this matches the hardware default.
+	 */
+	rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask,
+			       FIELD_PREP(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));
+
 	/* Disable access control to the CFGU */
 	writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
 
-- 
2.25.1

[PATCH 11/16] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support

[John Madieu]

Extend the link speed configuration to support Gen3 (8.0 GT/s) in addition
to Gen2 (5.0 GT/s). This is required for RZ/G3E PCIe host support, which is
Gen3 capable.

Instead of relying on DT max-link-speed for configuration, read the hardware
capabilities from the PCI_EXP_LNKCAP register to determine the maximum
supported speed. The DT max-link-speed property is now only used as an
optional limit when explicitly specified, which aligns with PCIe subsystem
expectations.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 26 ++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 18fccc687c6b..b0a5c08d2527 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -981,8 +981,9 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)
 {
 	u32 remote_supported_link_speeds, max_supported_link_speeds;
 	u32 cs2, tmp, pcie_cap = RZG3S_PCI_CFG_PCIEC;
-	u32 cur_link_speed, link_speed;
+	u32 cur_link_speed, link_speed, hw_max_speed;
 	u8 ltssm_state_l0 = 0xc;
+	u32 lnkcap;
 	int ret;
 	u16 ls;
 
@@ -1002,7 +1003,22 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)
 	ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA);
 	cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
 
-	switch (pcie_link_speed[host->max_link_speed]) {
+	/* Read hardware supported link speed from Link Capabilities Register */
+	lnkcap = readl_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKCAP);
+	hw_max_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lnkcap);
+
+	/*
+	 * Use DT max-link-speed only as a limit. If specified and lower
+	 * than hardware capability, cap to that value.
+	 */
+	if (host->max_link_speed > 0 && host->max_link_speed < hw_max_speed)
+		hw_max_speed = host->max_link_speed;
+
+	switch (pcie_link_speed[hw_max_speed]) {
+	case PCIE_SPEED_8_0GT:
+		max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_8_0GB - 1, 0);
+		link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
+		break;
 	case PCIE_SPEED_5_0GT:
 		max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0);
 		link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
@@ -1018,10 +1034,10 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)
 	remote_supported_link_speeds &= max_supported_link_speeds;
 
 	/*
-	 * Return if max link speed is already set or the connected device
+	 * Return if target link speed is already set or the connected device
 	 * doesn't support it.
 	 */
-	if (cur_link_speed == host->max_link_speed ||
+	if (cur_link_speed == hw_max_speed ||
 	    remote_supported_link_speeds != max_supported_link_speeds)
 		return 0;
 
@@ -1598,8 +1614,6 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	host->pcie = host->axi + RZG3S_PCI_CFG_BASE;
 
 	host->max_link_speed = of_pci_get_max_link_speed(np);
-	if (host->max_link_speed < 0)
-		host->max_link_speed = 2;
 
 	ret = rzg3s_pcie_host_parse_port(host);
 	if (ret)
-- 
2.25.1

[PATCH 12/16] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller

[John Madieu]

Add support for the PCIe controller found in RZ/G3E SoCs to the existing
RZ/G3S PCIe host driver. The RZ/G3E PCIe controller is similar to the
RZ/G3S's, with the following key differences:

 - Supports PCIe Gen3 (8.0 GT/s) link speeds alongside Gen2 (5.0 GT/s)
 - Uses a different reset control mechanism via AXI registers instead
   of the Linux reset framework
 - Requires specific SYSC configuration for link state control and
   Root Complex mode selection

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/pci/controller/pcie-rzg3s-host.c | 231 ++++++++++++++++++++---
 1 file changed, 209 insertions(+), 22 deletions(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index b0a5c08d2527..b046360e92da 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -111,6 +111,16 @@
 #define RZG3S_PCI_PERM_CFG_HWINIT_EN		BIT(2)
 #define RZG3S_PCI_PERM_PIPE_PHY_REG_EN		BIT(1)
 
+/* RZ/G3E specific registers */
+#define RZG3E_PCI_RESET				0x310
+#define RZG3E_PCI_RESET_RST_OUT_B		BIT(6)
+#define RZG3E_PCI_RESET_RST_PS_B		BIT(5)
+#define RZG3E_PCI_RESET_RST_LOAD_B		BIT(4)
+#define RZG3E_PCI_RESET_RST_CFG_B		BIT(3)
+#define RZG3E_PCI_RESET_RST_RSM_B		BIT(2)
+#define RZG3E_PCI_RESET_RST_GP_B		BIT(1)
+#define RZG3E_PCI_RESET_RST_B			BIT(0)
+
 #define RZG3S_PCI_MSIRE(id)			(0x600 + (id) * 0x10)
 #define RZG3S_PCI_MSIRE_ENA			BIT(0)
 
@@ -183,9 +193,13 @@ struct rzg3s_sysc_function {
 /**
  * struct rzg3s_sysc_info - RZ/G3S System Controller function info
  * @rst_rsm_b: Reset RSM_B function descriptor
+ * @l1_allow: L1 power state management function descriptor
+ * @mode: Mode configuration function descriptor
  */
 struct rzg3s_sysc_info {
 	struct rzg3s_sysc_function rst_rsm_b;
+	struct rzg3s_sysc_function l1_allow;
+	struct rzg3s_sysc_function mode;
 };
 
 /**
@@ -1201,6 +1215,10 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)
 	if (ret)
 		return ret;
 
+	/* Mandatory for RZ/G3E, harmless for RZ/G3S */
+	reset_control_bulk_assert(data->num_power_resets,
+				  host->power_resets);
+
 	return devm_reset_control_bulk_get_optional_exclusive(host->dev,
 							      data->num_cfg_resets,
 							      host->cfg_resets);
@@ -1266,6 +1284,7 @@ static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host)
 
 static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
 {
+	const struct rzg3s_sysc_info *sysc_info = host->sysc->info;
 	u32 val;
 	int ret;
 
@@ -1282,6 +1301,16 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
 	if (ret)
 		return ret;
 
+	/* Enable ASPM L1 transition for SoCs that use it */
+	if (sysc_info->l1_allow.mask) {
+		ret = regmap_update_bits(host->sysc->regmap,
+					 sysc_info->l1_allow.offset,
+					 sysc_info->l1_allow.mask,
+					 field_prep(sysc_info->l1_allow.mask, 1));
+		if (ret)
+			return ret;
+	}
+
 	/* Initialize the interrupts */
 	rzg3s_pcie_irq_init(host);
 
@@ -1625,12 +1654,27 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 		goto port_refclk_put;
 	}
 
-	ret = regmap_update_bits(sysc->regmap,
-				 sysc->info->rst_rsm_b.offset,
-				 sysc->info->rst_rsm_b.mask,
-				 field_prep(sysc->info->rst_rsm_b.mask, 1));
-	if (ret)
-		goto port_refclk_put;
+	/*
+	 * Put controller in RC (Root Complex) mode for SoCs that
+	 * support it. These can operate in either EP or RC mode.
+	 */
+	if (sysc->info->mode.mask) {
+		ret = regmap_write(sysc->regmap,
+				   sysc->info->mode.offset,
+				   sysc->info->mode.mask);
+		if (ret)
+			goto port_refclk_put;
+	}
+
+	/* De-assert SYSC RST_RSM_B only if used by the SoC */
+	if (sysc->info->rst_rsm_b.mask) {
+		ret = regmap_update_bits(sysc->regmap,
+					 sysc->info->rst_rsm_b.offset,
+					 sysc->info->rst_rsm_b.mask,
+					 field_prep(sysc->info->rst_rsm_b.mask, 1));
+		if (ret)
+			goto port_refclk_put;
+	}
 
 	ret = rzg3s_pcie_resets_prepare_and_get(host);
 	if (ret)
@@ -1684,9 +1728,11 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
 	 * SYSC RST_RSM_B signal need to be asserted before turning off the
 	 * power to the PHY.
 	 */
-	regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
-			   sysc->info->rst_rsm_b.mask,
-			   field_prep(sysc->info->rst_rsm_b.mask, 0));
+	if (sysc->info->rst_rsm_b.mask)
+		regmap_update_bits(sysc->regmap,
+				   sysc->info->rst_rsm_b.offset,
+				   sysc->info->rst_rsm_b.mask,
+				   field_prep(sysc->info->rst_rsm_b.mask, 0));
 port_refclk_put:
 	clk_put(host->port.refclk);
 
@@ -1721,11 +1767,15 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
 	if (ret)
 		goto cfg_reinit;
 
-	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
-				 sysc->info->rst_rsm_b.mask,
-				 field_prep(sysc->info->rst_rsm_b.mask, 0));
-	if (ret)
-		goto power_resets_restore;
+	/* Assert SYSC RST_RSM_B if supported */
+	if (sysc->info->rst_rsm_b.mask) {
+		ret = regmap_update_bits(sysc->regmap,
+					 sysc->info->rst_rsm_b.offset,
+					 sysc->info->rst_rsm_b.mask,
+					 field_prep(sysc->info->rst_rsm_b.mask, 0));
+		if (ret)
+			goto power_resets_restore;
+	}
 
 	return 0;
 
@@ -1748,11 +1798,23 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)
 	struct rzg3s_sysc *sysc = host->sysc;
 	int ret;
 
-	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
-				 sysc->info->rst_rsm_b.mask,
-				 field_prep(sysc->info->rst_rsm_b.mask, 1));
-	if (ret)
-		return ret;
+	/* De-assert SYSC RST_RSM_B if supported */
+	if (sysc->info->rst_rsm_b.mask) {
+		ret = regmap_update_bits(sysc->regmap,
+					 sysc->info->rst_rsm_b.offset,
+					 sysc->info->rst_rsm_b.mask,
+					 field_prep(sysc->info->rst_rsm_b.mask, 1));
+		if (ret)
+			return ret;
+	}
+
+	if (sysc->info->mode.mask) {
+		ret = regmap_write(sysc->regmap,
+				   sysc->info->mode.offset,
+				   sysc->info->mode.mask);
+		if (ret)
+			return ret;
+	}
 
 	ret = rzg3s_pcie_power_resets_deassert(host);
 	if (ret)
@@ -1779,12 +1841,133 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)
 	reset_control_bulk_assert(data->num_power_resets,
 				  host->power_resets);
 assert_rst_rsm_b:
-	regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
-			   sysc->info->rst_rsm_b.mask,
-			   field_prep(sysc->info->rst_rsm_b.mask, 0));
+	if (sysc->info->rst_rsm_b.mask)
+		regmap_update_bits(sysc->regmap,
+				   sysc->info->rst_rsm_b.offset,
+				   sysc->info->rst_rsm_b.mask,
+				   field_prep(sysc->info->rst_rsm_b.mask, 0));
 	return ret;
 }
 
+/* RZ/G3E SoC-specific implementations */
+static void rzg3e_pcie_config_pre_init(struct rzg3s_pcie_host *host)
+{
+	/*
+	 * De-assert LOAD_B and CFG_B during configuration phase.
+	 * These are part of the RZ/G3E reset register, not reset framework.
+	 * Other reset bits remain asserted until cfg_post_init.
+	 */
+	rzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,
+			       RZG3E_PCI_RESET_RST_LOAD_B | RZG3E_PCI_RESET_RST_CFG_B,
+			       RZG3E_PCI_RESET_RST_LOAD_B | RZG3E_PCI_RESET_RST_CFG_B);
+}
+
+static void rzg3e_cfg_deinit(struct rzg3s_pcie_host *host)
+{
+	writel_relaxed(0, host->axi + RZG3E_PCI_RESET);
+}
+
+static int rzg3e_cfg_post_init(struct rzg3s_pcie_host *host)
+{
+	/* De-assert PS_B, GP_B, RST_B */
+	rzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,
+			       RZG3E_PCI_RESET_RST_PS_B | RZG3E_PCI_RESET_RST_GP_B |
+			       RZG3E_PCI_RESET_RST_B,
+			       RZG3E_PCI_RESET_RST_PS_B | RZG3E_PCI_RESET_RST_GP_B |
+			       RZG3E_PCI_RESET_RST_B);
+
+	/* Hardware requires >= 500us delay before final reset deassert */
+	fsleep(500);
+
+	/* De-assert OUT_B and RSM_B to complete reset sequence */
+	rzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,
+			       RZG3E_PCI_RESET_RST_OUT_B | RZG3E_PCI_RESET_RST_RSM_B,
+			       RZG3E_PCI_RESET_RST_OUT_B | RZG3E_PCI_RESET_RST_RSM_B);
+
+	return 0;
+}
+
+static int rzg3e_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,
+					  struct resource_entry *entry,
+					  int *index)
+{
+	u64 pci_addr = entry->res->start - entry->offset;
+	u64 cpu_addr = entry->res->start;
+	u64 cpu_end = entry->res->end;
+	int id = *index;
+	u64 size;
+
+	/*
+	 * The RZ/G3E requires power-of-2 sizes (4K * 2^N) due to mask register
+	 * format. Split non-power-of-2 regions into multiple windows to avoid
+	 * over-mapping.
+	 */
+	while (cpu_addr <= cpu_end) {
+		u64 remaining_size = cpu_end - cpu_addr + 1;
+		u64 align_limit;
+
+		if (id >= RZG3S_MAX_WINDOWS)
+			return dev_err_probe(host->dev, -ENOSPC,
+					     "Failed to map inbound window for resource (%s)\n",
+					     entry->res->name);
+
+		/* Start with largest power-of-two that fits in remaining size */
+		size = 1ULL << __fls(remaining_size);
+
+		/*
+		 * Find alignment limit - the largest power-of-two that both
+		 * addresses are aligned to
+		 */
+		align_limit = min(cpu_addr ? (1ULL << __ffs(cpu_addr)) : ~0ULL,
+				  pci_addr ? (1ULL << __ffs(pci_addr)) : ~0ULL);
+
+		/* Window size cannot exceed alignment */
+		size = min(size, align_limit);
+
+		/*
+		 * According to the RZ/G3E HW manual Rev.1.15,
+		 * (Section 6.6.4.1.3.(74) AXI Window Mask (Lower) Register):
+		 * The area which can be set is 4K * 2^N bytes.
+		 */
+		size = max(size, SZ_4K);
+
+		/*
+		 * HW expects size - 1 for mask register.
+		 * For example: 4KB (0x1000) becomes mask 0xfff (12 bits set).
+		 */
+		rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr,
+					      size - 1, id);
+
+		cpu_addr += size;
+		pci_addr += size;
+		id++;
+	}
+	*index = id;
+
+	return 0;
+}
+
+static const char * const rzg3e_soc_power_resets[] = { "aresetn" };
+
+static const struct rzg3s_pcie_soc_data rzg3e_soc_data = {
+	.power_resets = rzg3e_soc_power_resets,
+	.num_power_resets = ARRAY_SIZE(rzg3e_soc_power_resets),
+	.cfg_post_init = rzg3e_cfg_post_init,
+	.cfg_deinit = rzg3e_cfg_deinit,
+	.cfg_pre_init = rzg3e_pcie_config_pre_init,
+	.set_inbound_windows = rzg3e_pcie_set_inbound_windows,
+	.sysc_info = {
+		.l1_allow = {
+			.offset = 0x1020,
+			.mask = BIT(0),
+		},
+		.mode = {
+			.offset = 0x1024,
+			.mask = BIT(0),
+		},
+	},
+};
+
 static const struct dev_pm_ops rzg3s_pcie_pm_ops = {
 	NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq,
 				  rzg3s_pcie_resume_noirq)
@@ -1819,6 +2002,10 @@ static const struct of_device_id rzg3s_pcie_of_match[] = {
 		.compatible = "renesas,r9a08g045-pcie",
 		.data = &rzg3s_soc_data,
 	},
+	{
+		.compatible = "renesas,r9a09g047-pcie",
+		.data = &rzg3e_soc_data,
+	},
 	{}
 };
 
-- 
2.25.1

[PATCH 13/16] arm64: dts: renesas: r9a09g047: Add PCIe node

[John Madieu]

The RZ/G3E SoC family features an x2 PCIe IP. Add the PCIe node.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index cbb48ff5028f..1625fa1f8bd4 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -841,6 +841,74 @@ wdt3: watchdog@13000400 {
 			status = "disabled";
 		};
 
+		pcie: pcie@13400000 {
+			compatible = "renesas,r9a09g047-pcie";
+			reg = <0 0x13400000 0 0x10000>;
+			ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
+				 <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>;
+			bus-range = <0x0 0xff>;
+			interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "all", "inta", "intb", "intc",
+					  "intd", "msi", "link_bandwidth",
+					  "link_equalization_request", "pm_pme",
+					  "serr", "serr_cor", "serr_nonfatal",
+					  "serr_fatal", "dma", "pcie_evt",
+					  "axi_err", "msg", "turn_off_event",
+					  "pmu_poweroff", "d3_event_f0",
+					  "d3_event_f1", "cfg_pmcsr_writeclear_f0",
+					  "cfg_pmcsr_writeclear_f1";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
+					<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
+					<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
+					<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
+			clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>;
+			clock-names = "aclk", "pmu";
+			resets = <&cpg 0xb2>;
+			reset-names = "aresetn";
+			power-domains = <&cpg>;
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			renesas,sysc = <&sys>;
+			status = "disabled";
+
+			pcie_port0: pcie@0,0 {
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				ranges;
+				device_type = "pci";
+				vendor-id = <0x1912>;
+				device-id = <0x0039>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+			};
+		};
+
 		tsu: thermal@14002000 {
 			compatible = "renesas,r9a09g047-tsu";
 			reg = <0 0x14002000 0 0x1000>;
-- 
2.25.1

[PATCH 14/16] arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock

[John Madieu]

The RZ/G3E SMARC SoM has a fixed 100 MHz reference clock generator
for PCIe. Model it as a fixed-clock and assign it to the PCIe port.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index eb0de21d6716..7e2345bb9918 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -43,6 +43,12 @@ memory@48000000 {
 		reg = <0x0 0x48000000 0x0 0xf8000000>;
 	};
 
+	pcie_refclk: clock-pcie-ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
@@ -168,6 +174,11 @@ phy1: ethernet-phy@7 {
 	};
 };
 
+&pcie_port0 {
+	clocks = <&pcie_refclk>;
+	clock-names = "ref";
+};
+
 &pinctrl {
 	eth0_pins: eth0 {
 		clk {
-- 
2.25.1

[PATCH 15/16] arm64: dts: renesas: r9a09g047e57-smarc: Add PCIe pincontrol

[John Madieu]

Add pincontrol configuration for PCIe on the RZ/G3E SMARC platform.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 696903dc7a63..a9e58103d496 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -167,6 +167,17 @@ rsci9_pins: rsci9 {
 		bias-pull-up;
 	};
 
+	pcie-clkreq-n {
+		gpio-hog;
+		gpios = <RZG3E_GPIO(4, 5) GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "pcie_clkreq_n";
+	};
+
+	pcie_pins: pcie {
+		pinmux = <RZG3E_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
+	};
+
 	scif_pins: scif {
 		pins = "SCIF_TXD", "SCIF_RXD";
 		renesas,output-impedance = <1>;
-- 
2.25.1

[PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

[John Madieu]

The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
Enable PCIe support.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index b607b5d6c259..3db7d31be2b2 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -96,6 +96,13 @@ &i2c0 {
 	clock-frequency = <400000>;
 };
 
+&pcie {
+	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
+	pinctrl-0 = <&pcie_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &scif0 {
 	status = "okay";
 };
-- 
2.25.1

RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

[Biju Das]

Hi John Madieu,

Thanks for the patch.

> -----Original Message-----
> From: John Madieu <john.madieu.xa@bp.renesas.com>
> Sent: 14 January 2026 15:34
> Subject: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
> 
> The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
> Enable PCIe support.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-
> smarc2.dtsi
> index b607b5d6c259..3db7d31be2b2 100644
> --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> @@ -96,6 +96,13 @@ &i2c0 {
>  	clock-frequency = <400000>;
>  };
> 
> +&pcie {
> +	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;

This entry to be only in SoC dtsi like RZ/G3S.

> +	pinctrl-0 = <&pcie_pins>;
> +	pinctrl-names = "default";

The pinctrl entries to be moved to board specific file as 
it will be used by RZ/G3S, RZ/G3E and Upcoming SoC in future.

Cheers,
Biju

> +	status = "okay";
> +};
> +
>  &scif0 {
>  	status = "okay";
>  };
> --
> 2.25.1

RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

[John Madieu]

Hi Biju,

Thanks for the feedback.

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: Wednesday, January 14, 2026 5:20 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Subject: RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable
> PCIe
> 
> Hi John Madieu,
> 
> Thanks for the patch.
> 
> > -----Original Message-----
> > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > Sent: 14 January 2026 15:34
> > Subject: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable
> > PCIe
> >
> > The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
> > Enable PCIe support.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > b/arch/arm64/boot/dts/renesas/renesas-
> > smarc2.dtsi
> > index b607b5d6c259..3db7d31be2b2 100644
> > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > @@ -96,6 +96,13 @@ &i2c0 {
> >  	clock-frequency = <400000>;
> >  };
> >
> > +&pcie {
> > +	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
> 
> This entry to be only in SoC dtsi like RZ/G3S.
> 
> > +	pinctrl-0 = <&pcie_pins>;
> > +	pinctrl-names = "default";
> 
> The pinctrl entries to be moved to board specific file as it will be used
> by RZ/G3S, RZ/G3E and Upcoming SoC in future.
> 

To summarize, you suggest me to keep only the dma-ranges update in this
file and move pinctrl assignment into r9a09g047e57-smarc.dts right ?

> Cheers,
> Biju
> 
Regards,
John

> > +	status = "okay";
> > +};
> > +
> >  &scif0 {
> >  	status = "okay";
> >  };
> > --
> > 2.25.1

RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

[Biju Das]

> -----Original Message-----
> From: John Madieu <john.madieu.xa@bp.renesas.com>
> Sent: 14 January 2026 16:35
> To: Biju Das <biju.das.jz@bp.renesas.com>; Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Cc: robh@kernel.org; bhelgaas@google.com; conor+dt@kernel.org; magnus.damm <magnus.damm@gmail.com>;
> linux-pci@vger.kernel.org; linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> clk@vger.kernel.org; john.madieu@gmail.com
> Subject: RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
> 
> Hi Biju,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> > Sent: Wednesday, January 14, 2026 5:20 PM
> > To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> > <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> > kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> > krzk+dt@kernel.org
> > Subject: RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc:
> > Enable PCIe
> >
> > Hi John Madieu,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > > Sent: 14 January 2026 15:34
> > > Subject: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc:
> > > Enable PCIe
> > >
> > > The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
> > > Enable PCIe support.
> > >
> > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > ---
> > >  arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > b/arch/arm64/boot/dts/renesas/renesas-
> > > smarc2.dtsi
> > > index b607b5d6c259..3db7d31be2b2 100644
> > > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > @@ -96,6 +96,13 @@ &i2c0 {
> > >  	clock-frequency = <400000>;
> > >  };
> > >
> > > +&pcie {
> > > +	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
> >
> > This entry to be only in SoC dtsi like RZ/G3S.
> >
> > > +	pinctrl-0 = <&pcie_pins>;
> > > +	pinctrl-names = "default";
> >
> > The pinctrl entries to be moved to board specific file as it will be
> > used by RZ/G3S, RZ/G3E and Upcoming SoC in future.
> >
> 
> To summarize, you suggest me to keep only the dma-ranges update in this file and move pinctrl
> assignment into r9a09g047e57-smarc.dts right ?

Just "status" should be sufficient. Drop dma-ranges and move the pinctrl entries to board dts.

Cheers,
Biju

RE: [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support

[Biju Das]

Hi John,

Thnaks for the patch.

> -----Original Message-----
> From: John Madieu <john.madieu.xa@bp.renesas.com>
> Sent: 14 January 2026 15:33
> Subject: [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support
> 
> The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with the existing RZ/G3S
> PCIe controller, but with several key differences.
> This series adds support for the RZ/G3E PCIe controller by extending the existing RZ/G3S driver and
> device tree bindings.
> 
> Key differences between RZ/G3E and RZ/G3S PCIe controllers:
> 
> Link Speed Support:
>  - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s)
>  - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only
> 
> Reset Control:
>  - RZ/G3E: Uses register-based reset control mechanism
>  - RZ/G3S: Uses exclusively external reset control signals
> 
> Inbound Window Configuration:
>  - RZ/G3E: Requires precise power-of-2 window coverage with strict address
>    alignment constraints. Non-power-of-2 memory regions must be split into
>    multiple windows to avoid over-mapping, ensuring proper hardware address
>    decoding for DMA operations.
>  - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-2,
>    creating single larger windows. The hardware tolerates over-mapped regions.
> 
> Class/Revision IDs:
>  - RZ/G3E: Requires explicit setting of class/revision values
>  - RZ/G3S: Has default values in hardware
> 
> Clock Naming:
>  - RZ/G3E: Uses "clkpmu" PM control clock while CLKREQ_B is deasserting
>  - RZ/G3S: Uses "clkl1pm" clock for power management

Typo: RZ/G3S and RZ/G3E swapped. FYI, the upcoming SoC has both clocks.

Cheers,
Biju 

> 
> Phy Settings:
>  - RZ/G3E: Does not need PHY settings as it works with default hw values
>  - RZ/G3S: Requires explicit PHY settings
> 
> This series extends the existing driver to detect the SoC type from the device tree compatible string
> and configure the controller appropriately. The updates are minimal and focused on the hardware-
> specific differences while keeping the common code paths unified.
> 
> Note: The clks "PCIE_0_REFCLK_IN" and "PCIE_0_CORECLKIN" are added by mistake in hardware manual
> 
> John Madieu (16):
>   PCI: rzg3s-host: Fix reset handling in probe error path
>   PCI: rzg3s-host: Fix inbound window size tracking
>   clk: renesas: rzv2h-cpg: Add support for init_off clocks
>   clk: renesas: r9a09g047: Add PCIe clocks and reset
>   dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
>   PCI: rzg3s-host: Make SYSC register offsets SoC-specific
>   PCI: rzg3s-host: Make configuration reset lines optional
>   PCI: rzg3s-host: Make inbound window setup SoC-specific
>   PCI: rzg3s-host: Add SoC-specific configuration and initialization
>     callbacks
>   PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
>   PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
>   PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
>   arm64: dts: renesas: r9a09g047: Add PCIe node
>   arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
>   arm64: dts: renesas: r9a09g047e57-smarc: Add PCIe pincontrol
>   arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
> 
>  .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243 +++++++----
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  68 +++
>  .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  11 +
>  .../boot/dts/renesas/renesas-smarc2.dtsi      |   7 +
>  .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  11 +
>  drivers/clk/renesas/r9a09g047-cpg.c           |   5 +
>  drivers/clk/renesas/rzv2h-cpg.c               |   9 +
>  drivers/clk/renesas/rzv2h-cpg.h               |  18 +-
>  drivers/pci/controller/pcie-rzg3s-host.c      | 393 +++++++++++++++---
>  9 files changed, 632 insertions(+), 133 deletions(-)
> 
> --
> 2.25.1

Re: [PATCH 07/16] PCI: rzg3s-host: Make configuration reset lines optional

[Bjorn Helgaas]

On Wed, Jan 14, 2026 at 04:33:28PM +0100, John Madieu wrote:
> Some SoC variants such as RZ/G3E handles configuration reset control
> through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets
> optional by using devm_reset_control_bulk_get_optional_exclusive() to allow
> SoCs to use alternative or complementaty reset control mechanisms.

s/handles/handle/
s/complementaty/complementary/

Re: [PATCH 09/16] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks

[Bjorn Helgaas]

On Wed, Jan 14, 2026 at 04:33:30PM +0100, John Madieu wrote:
> Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks
> to handle SoC-specific configuration methods. While RZ/G3S uses the Linux
> reset framework with dedicated reset lines, other SoC variants like RZ/G3E
> control configuration resets through PCIe AXI registers.
> 
> As Linux reset bulk API gracefully handles optional NULL reset lines
> (num_cfg_resets = 0 for RZ/G3E), the driver continues to use the standard
> reset framework when reset lines are available, while custom callbacks
> are only invoked when provided.
> 
> This provides a balanced pattern where:
> - RZ/G3S: Uses reset framework only, no callbacks needed
> - RZ/G3E: Sets num_cfg_resets=0, provides cfg_pre_init/cfg_post_init/cfg_deinit
> - In addition to that, RZ/G3E requires explicit cfg reset and clok turned off
>   to put the PCIe IP in a known state.

s/clok/clock/

RE: [PATCH 09/16] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks

[John Madieu]

Hi Bjorn,

Thanks for the feedback.

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Wednesday, January 14, 2026 11:41 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 09/16] PCI: rzg3s-host: Add SoC-specific configuration
> and initialization callbacks
> 
> On Wed, Jan 14, 2026 at 04:33:30PM +0100, John Madieu wrote:
> > Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks to
> > handle SoC-specific configuration methods. While RZ/G3S uses the Linux
> > reset framework with dedicated reset lines, other SoC variants like
> > RZ/G3E control configuration resets through PCIe AXI registers.
> >
> > As Linux reset bulk API gracefully handles optional NULL reset lines
> > (num_cfg_resets = 0 for RZ/G3E), the driver continues to use the
> > standard reset framework when reset lines are available, while custom
> > callbacks are only invoked when provided.
> >
> > This provides a balanced pattern where:
> > - RZ/G3S: Uses reset framework only, no callbacks needed
> > - RZ/G3E: Sets num_cfg_resets=0, provides
> > cfg_pre_init/cfg_post_init/cfg_deinit
> > - In addition to that, RZ/G3E requires explicit cfg reset and clok
> turned off
> >   to put the PCIe IP in a known state.
> 
> s/clok/clock/

Noted for v2.

Regards,
John

RE: [PATCH 07/16] PCI: rzg3s-host: Make configuration reset lines optional

[John Madieu]

Hi Bjorn,

Thanks for the feedback.

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Wednesday, January 14, 2026 11:38 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 07/16] PCI: rzg3s-host: Make configuration reset lines
> optional
> 
> On Wed, Jan 14, 2026 at 04:33:28PM +0100, John Madieu wrote:
> > Some SoC variants such as RZ/G3E handles configuration reset control
> > through PCIe AXI registers instead of dedicated reset lines. Make
> > cfg_resets optional by using
> > devm_reset_control_bulk_get_optional_exclusive() to allow SoCs to use
> alternative or complementaty reset control mechanisms.
> 
> s/handles/handle/
> s/complementaty/complementary/

Thanks for pointing that out.
Will update in v2.

Regards,
John

RE: [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller support

[John Madieu]

Hi Biju,

Thanks for the feedback.

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: Wednesday, January 14, 2026 6:48 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Subject: RE: [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller
> support
> 
> Hi John,
> 
> Thnaks for the patch.
> 
> > -----Original Message-----
> > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > Sent: 14 January 2026 15:33
> > Subject: [PATCH 00/16] PCI: renesas: Add RZ/G3E PCIe controller
> > support
> >
> > The Renesas RZ/G3E SoC features a PCIe controller that shares
> > similarities with the existing RZ/G3S PCIe controller, but with several
> key differences.
> > This series adds support for the RZ/G3E PCIe controller by extending
> > the existing RZ/G3S driver and device tree bindings.
> >
> > Key differences between RZ/G3E and RZ/G3S PCIe controllers:
> >
> > Link Speed Support:
> >  - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s)
> >  - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only
> >
> > Reset Control:
> >  - RZ/G3E: Uses register-based reset control mechanism
> >  - RZ/G3S: Uses exclusively external reset control signals
> >
> > Inbound Window Configuration:
> >  - RZ/G3E: Requires precise power-of-2 window coverage with strict
> address
> >    alignment constraints. Non-power-of-2 memory regions must be split
> into
> >    multiple windows to avoid over-mapping, ensuring proper hardware
> address
> >    decoding for DMA operations.
> >  - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-
> 2,
> >    creating single larger windows. The hardware tolerates over-mapped
> regions.
> >
> > Class/Revision IDs:
> >  - RZ/G3E: Requires explicit setting of class/revision values
> >  - RZ/G3S: Has default values in hardware
> >
> > Clock Naming:
> >  - RZ/G3E: Uses "clkpmu" PM control clock while CLKREQ_B is
> > deasserting
> >  - RZ/G3S: Uses "clkl1pm" clock for power management
> 
> Typo: RZ/G3S and RZ/G3E swapped. FYI, the upcoming SoC has both clocks.
> 

Indeed. I'll swap that back in v2's CL.

Regards,
John 

> Cheers,
> Biju
> 
> >
> > Phy Settings:
> >  - RZ/G3E: Does not need PHY settings as it works with default hw
> > values
> >  - RZ/G3S: Requires explicit PHY settings
> >
> > This series extends the existing driver to detect the SoC type from
> > the device tree compatible string and configure the controller
> > appropriately. The updates are minimal and focused on the hardware-
> specific differences while keeping the common code paths unified.
> >
> > Note: The clks "PCIE_0_REFCLK_IN" and "PCIE_0_CORECLKIN" are added by
> > mistake in hardware manual
> >
> > John Madieu (16):
> >   PCI: rzg3s-host: Fix reset handling in probe error path
> >   PCI: rzg3s-host: Fix inbound window size tracking
> >   clk: renesas: rzv2h-cpg: Add support for init_off clocks
> >   clk: renesas: r9a09g047: Add PCIe clocks and reset
> >   dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
> >   PCI: rzg3s-host: Make SYSC register offsets SoC-specific
> >   PCI: rzg3s-host: Make configuration reset lines optional
> >   PCI: rzg3s-host: Make inbound window setup SoC-specific
> >   PCI: rzg3s-host: Add SoC-specific configuration and initialization
> >     callbacks
> >   PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
> >   PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
> >   PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
> >   arm64: dts: renesas: r9a09g047: Add PCIe node
> >   arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
> >   arm64: dts: renesas: r9a09g047e57-smarc: Add PCIe pincontrol
> >   arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
> >
> >  .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243 +++++++----
> >  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  68 +++
> >  .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  11 +
> >  .../boot/dts/renesas/renesas-smarc2.dtsi      |   7 +
> >  .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  11 +
> >  drivers/clk/renesas/r9a09g047-cpg.c           |   5 +
> >  drivers/clk/renesas/rzv2h-cpg.c               |   9 +
> >  drivers/clk/renesas/rzv2h-cpg.h               |  18 +-
> >  drivers/pci/controller/pcie-rzg3s-host.c      | 393 +++++++++++++++---
> >  9 files changed, 632 insertions(+), 133 deletions(-)
> >
> > --
> > 2.25.1

Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[claudiu beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Fix incorrect reset_control_bulk_deassert() call in the probe error
> path. When unwinding from a failed pci_host_probe(), the configuration
> resets should be asserted to restore the hardware to its initial state,
> not deasserted again.
> 
> Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver")
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 5aa58638903f..c1053f95bc95 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   
>   host_probe_teardown:
>   	rzg3s_pcie_teardown_irqdomain(host);
> -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> +	reset_control_bulk_assert(host->data->num_cfg_resets,
>   				    host->cfg_resets);

This now fits on an 80 chars line, could you please update it like:

	reset_control_bulk_assert(host->data->num_cfg_resets, host->cfg_resets);

Thank you,
Claudiu

Re: [PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC

[Krzysztof Kozlowski]

On Wed, Jan 14, 2026 at 04:33:26PM +0100, John Madieu wrote:
> Extend the existing device tree bindings for Renesas RZ/G3S PCIe
> controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
> controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
> differences:
> 
>  - Uses a different device ID
>  - Supports PCIe Gen3 (8.0 GT/s) link speeds
>  - Uses a different clock naming (clkpmu vs clkl1pm)
>  - Has a different set of interrupts, interrupt ordering, and reset signals
> 
> Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>  .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243 +++++++++++++-----
>  1 file changed, 172 insertions(+), 71 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> index d668782546a2..c68bc76af35d 100644
> --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> @@ -10,85 +10,34 @@ maintainers:
>    - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>  
>  description:
> -  Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
> -  4.0 and supports up to 5 GT/s (Gen2).
> +  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
> +  Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
> +  up to 8 GT/s (Gen3) for RZ/G3E.
>  
>  properties:
>    compatible:
> -    const: renesas,r9a08g045-pcie # RZ/G3S
> +    enum:
> +      - renesas,r9a08g045-pcie # RZ/G3S
> +      - renesas,r9a09g047-pcie # RZ/G3E
>  
>    reg:
>      maxItems: 1
>  
> -  interrupts:
> -    items:

Same review as already in the past for Renesas. Broadest constraints
always stay here and list should share items.

> -      - description: System error interrupt
> -      - description: System error on correctable error interrupt
> -      - description: System error on non-fatal error interrupt
> -      - description: System error on fatal error interrupt
> -      - description: AXI error interrupt
> -      - description: INTA interrupt
> -      - description: INTB interrupt
> -      - description: INTC interrupt
> -      - description: INTD interrupt
> -      - description: MSI interrupt
> -      - description: Link bandwidth interrupt
> -      - description: PME interrupt
> -      - description: DMA interrupt
> -      - description: PCIe event interrupt
> -      - description: Message interrupt
> -      - description: All interrupts
> -
> -  interrupt-names:
> -    items:
> -      - description: serr
> -      - description: ser_cor
> -      - description: serr_nonfatal
> -      - description: serr_fatal
> -      - description: axi_err
> -      - description: inta
> -      - description: intb
> -      - description: intc
> -      - description: intd
> -      - description: msi
> -      - description: link_bandwidth
> -      - description: pm_pme
> -      - description: dma
> -      - description: pcie_evt
> -      - description: msg
> -      - description: all
> +  interrupts: true
> +
> +  interrupt-names: true
>  
>    interrupt-controller: true
>  
>    clocks:
> -    items:
> -      - description: System clock
> -      - description: PM control clock
> +    maxItems: 2
>  
>    clock-names:
> -    items:
> -      - description: aclk
> -      - description: pm
> -
> -  resets:
> -    items:
> -      - description: AXI2PCIe Bridge reset
> -      - description: Data link layer/transaction layer reset
> -      - description: Transaction layer (ACLK domain) reset
> -      - description: Transaction layer (PCLK domain) reset
> -      - description: Physical layer reset
> -      - description: Configuration register reset
> -      - description: Configuration register reset
> -
> -  reset-names:
> -    items:
> -      - description: aresetn
> -      - description: rst_b
> -      - description: rst_gp_b
> -      - description: rst_ps_b
> -      - description: rst_rsm_b
> -      - description: rst_cfg_b
> -      - description: rst_load_b
> +    maxItems: 2
> +
> +  resets: true
> +
> +  reset-names: true
>  
>    power-domains:
>      maxItems: 1
> @@ -128,11 +77,12 @@ patternProperties:
>          const: 0x1912
>  
>        device-id:
> -        const: 0x0033
> +        enum:
> +          - 0x0033
> +          - 0x0039
>  
>        clocks:
> -        items:
> -          - description: Reference clock
> +        maxItems: 1
>  
>        clock-names:
>          items:
> @@ -142,8 +92,6 @@ patternProperties:
>        - device_type
>        - vendor-id
>        - device-id
> -      - clocks
> -      - clock-names
>  
>      unevaluatedProperties: false
>  
> @@ -167,6 +115,159 @@ required:
>  
>  allOf:
>    - $ref: /schemas/pci/pci-host-bridge.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a08g045-pcie
> +    then:
> +      properties:
> +        interrupts:
> +          items:
> +            - description: System error interrupt
> +            - description: System error on correctable error interrupt
> +            - description: System error on non-fatal error interrupt
> +            - description: System error on fatal error interrupt
> +            - description: AXI error interrupt
> +            - description: INTA interrupt
> +            - description: INTB interrupt
> +            - description: INTC interrupt
> +            - description: INTD interrupt
> +            - description: MSI interrupt
> +            - description: Link bandwidth interrupt
> +            - description: PME interrupt
> +            - description: DMA interrupt
> +            - description: PCIe event interrupt
> +            - description: Message interrupt
> +            - description: All interrupts
> +        interrupt-names:
> +          items:
> +            - const: serr

So serr is first...

> +            - const: serr_cor
> +            - const: serr_nonfatal
> +            - const: serr_fatal
> +            - const: axi_err
> +            - const: inta
> +            - const: intb
> +            - const: intc
> +            - const: intd
> +            - const: msi
> +            - const: link_bandwidth
> +            - const: pm_pme
> +            - const: dma
> +            - const: pcie_evt
> +            - const: msg
> +            - const: all
> +        clocks:
> +          items:
> +            - description: System clock
> +            - description: PM control clock
> +        clock-names:
> +          items:
> +            - const: aclk
> +            - const: pm
> +        resets:
> +          items:
> +            - description: AXI2PCIe Bridge reset
> +            - description: Data link layer/transaction layer reset
> +            - description: Transaction layer (ACLK domain) reset
> +            - description: Transaction layer (PCLK domain) reset
> +            - description: Physical layer reset
> +            - description: Configuration register reset
> +            - description: Configuration register reset
> +        reset-names:
> +          items:
> +            - const: aresetn
> +            - const: rst_b
> +            - const: rst_gp_b
> +            - const: rst_ps_b
> +            - const: rst_rsm_b
> +            - const: rst_cfg_b
> +            - const: rst_load_b
> +      patternProperties:
> +        "^pcie@0,[0-0]$":
> +          properties:
> +            device-id:
> +              const: 0x0033
> +          required:
> +            - clocks
> +            - clock-names
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g047-pcie
> +    then:
> +      properties:
> +        interrupts:
> +          items:
> +            - description: All interrupts
> +            - description: INTA interrupt
> +            - description: INTB interrupt
> +            - description: INTC interrupt
> +            - description: INTD interrupt
> +            - description: MSI interrupt
> +            - description: Link bandwidth interrupt
> +            - description: Link equalization request interrupt
> +            - description: PME interrupt
> +            - description: System error interrupt
> +            - description: System error on correctable error interrupt
> +            - description: System error on non-fatal error interrupt
> +            - description: System error on fatal error interrupt
> +            - description: DMA interrupt
> +            - description: PCIe event interrupt
> +            - description: AXI error interrupt
> +            - description: Message interrupt
> +            - description: Turn off event interrupt
> +            - description: PMU power off interrupt
> +            - description: D3 event function 0 interrupt
> +            - description: D3 event function 1 interrupt
> +            - description: Configuration PMCSR write clear function 0 interrupt
> +            - description: Configuration PMCSR write clear function 1 interrupt
> +        interrupt-names:
> +          items:
> +            - const: all
> +            - const: inta
> +            - const: intb
> +            - const: intc
> +            - const: intd
> +            - const: msi
> +            - const: link_bandwidth
> +            - const: link_equalization_request
> +            - const: pm_pme
> +            - const: serr

And middle? What sort of mess is this?

Please learn from existing review, organize internal knowledge so we
won't be repeating the same.

I am not reviewing the rest.

Best regards,
Krzysztof

Re: [PATCH 10/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility

[kernel test robot]

Hi John,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20260114]
[cannot apply to pci/next pci/for-linus geert-renesas-devel/next geert-renesas-drivers/renesas-clk linus/master v6.19-rc5 v6.19-rc4 v6.19-rc3 v6.19-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/John-Madieu/PCI-rzg3s-host-Fix-reset-handling-in-probe-error-path/20260114-234634
base:   next-20260114
patch link:    https://lore.kernel.org/r/20260114153337.46765-11-john.madieu.xa%40bp.renesas.com
patch subject: [PATCH 10/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
config: powerpc64-randconfig-002-20260115 (https://download.01.org/0day-ci/archive/20260115/202601152104.pV9uMS76-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260115/202601152104.pV9uMS76-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601152104.pV9uMS76-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/pcie-rzg3s-host.c:1090:11: warning: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((mask), char: (unsigned char)0, unsigned char: (unsigned char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long long: (unsigned long long)0, long long: (unsigned long long)0, default: (mask)))' (aka 'unsigned int') is always false [-Wtautological-constant-out-of-range-compare]
    1090 |                                FIELD_PREP(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));
         |                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:137:3: note: expanded from macro 'FIELD_PREP'
     137 |                 __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: ");      \
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:79:50: note: expanded from macro '__BF_FIELD_CHECK_REG'
      79 |         BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) >               \
         |         ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~
      80 |                          __bf_cast_unsigned(reg, ~0ull),                \
         |                          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      81 |                          pfx "type of reg too small for mask")
         |                          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:58: note: expanded from macro 'BUILD_BUG_ON_MSG'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~
   include/linux/compiler_types.h:667:22: note: expanded from macro 'compiletime_assert'
     667 |         _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |         ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler_types.h:655:23: note: expanded from macro '_compiletime_assert'
     655 |         __compiletime_assert(condition, msg, prefix, suffix)
         |         ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/compiler_types.h:647:9: note: expanded from macro '__compiletime_assert'
     647 |                 if (!(condition))                                       \
         |                       ^~~~~~~~~
   1 warning generated.


vim +1090 drivers/pci/controller/pcie-rzg3s-host.c

  1057	
  1058	static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
  1059	{
  1060		struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
  1061		u32 mask = GENMASK(31, 8);
  1062		struct resource_entry *ft;
  1063		struct resource *bus;
  1064		u8 subordinate_bus;
  1065		u8 secondary_bus;
  1066		u8 primary_bus;
  1067	
  1068		ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
  1069		if (!ft)
  1070			return -ENODEV;
  1071	
  1072		bus = ft->res;
  1073		primary_bus = bus->start;
  1074		secondary_bus = bus->start + 1;
  1075		subordinate_bus = bus->end;
  1076	
  1077		/* Enable access control to the CFGU */
  1078		writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
  1079			       host->axi + RZG3S_PCI_PERM);
  1080	
  1081		/* HW manual recommends to write 0xffffffff on initialization */
  1082		writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
  1083		writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
  1084	
  1085		/*
  1086		 * Explicitly program class code. RZ/G3E requires this configuration.
  1087		 * Harmless for RZ/G3S where this matches the hardware default.
  1088		 */
  1089		rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask,
> 1090				       FIELD_PREP(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));
  1091	
  1092		/* Disable access control to the CFGU */
  1093		writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
  1094	
  1095		/* Update bus info */
  1096		writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
  1097		writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
  1098		writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
  1099	
  1100		return 0;
  1101	}
  1102	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC

[claudiu beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Extend the existing device tree bindings for Renesas RZ/G3S PCIe
> controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
> controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
> differences:
> 
>   - Uses a different device ID
>   - Supports PCIe Gen3 (8.0 GT/s) link speeds
>   - Uses a different clock naming (clkpmu vs clkl1pm)
>   - Has a different set of interrupts, interrupt ordering, and reset signals
> 
> Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243 +++++++++++++-----
>   1 file changed, 172 insertions(+), 71 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> index d668782546a2..c68bc76af35d 100644
> --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> @@ -10,85 +10,34 @@ maintainers:
>     - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>   
>   description:
> -  Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
> -  4.0 and supports up to 5 GT/s (Gen2).
> +  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
> +  Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
> +  up to 8 GT/s (Gen3) for RZ/G3E.
>   
>   properties:
>     compatible:
> -    const: renesas,r9a08g045-pcie # RZ/G3S
> +    enum:
> +      - renesas,r9a08g045-pcie # RZ/G3S
> +      - renesas,r9a09g047-pcie # RZ/G3E
>   
>     reg:
>       maxItems: 1
>   
> -  interrupts:
> -    items:
> -      - description: System error interrupt
> -      - description: System error on correctable error interrupt
> -      - description: System error on non-fatal error interrupt
> -      - description: System error on fatal error interrupt
> -      - description: AXI error interrupt
> -      - description: INTA interrupt
> -      - description: INTB interrupt
> -      - description: INTC interrupt
> -      - description: INTD interrupt
> -      - description: MSI interrupt
> -      - description: Link bandwidth interrupt
> -      - description: PME interrupt
> -      - description: DMA interrupt
> -      - description: PCIe event interrupt
> -      - description: Message interrupt
> -      - description: All interrupts
> -
> -  interrupt-names:
> -    items:
> -      - description: serr
> -      - description: ser_cor
> -      - description: serr_nonfatal
> -      - description: serr_fatal
> -      - description: axi_err
> -      - description: inta
> -      - description: intb
> -      - description: intc
> -      - description: intd
> -      - description: msi
> -      - description: link_bandwidth
> -      - description: pm_pme
> -      - description: dma
> -      - description: pcie_evt
> -      - description: msg
> -      - description: all
> +  interrupts: true
> +
> +  interrupt-names: true
>   
>     interrupt-controller: true
>   
>     clocks:
> -    items:
> -      - description: System clock
> -      - description: PM control clock
> +    maxItems: 2
>   
>     clock-names:
> -    items:
> -      - description: aclk
> -      - description: pm
> -
> -  resets:
> -    items:
> -      - description: AXI2PCIe Bridge reset
> -      - description: Data link layer/transaction layer reset
> -      - description: Transaction layer (ACLK domain) reset
> -      - description: Transaction layer (PCLK domain) reset
> -      - description: Physical layer reset
> -      - description: Configuration register reset
> -      - description: Configuration register reset
> -
> -  reset-names:
> -    items:
> -      - description: aresetn
> -      - description: rst_b
> -      - description: rst_gp_b
> -      - description: rst_ps_b
> -      - description: rst_rsm_b
> -      - description: rst_cfg_b
> -      - description: rst_load_b
> +    maxItems: 2
> +
> +  resets: true
> +
> +  reset-names: true
>   
>     power-domains:
>       maxItems: 1
> @@ -128,11 +77,12 @@ patternProperties:
>           const: 0x1912
>   
>         device-id:
> -        const: 0x0033
> +        enum:
> +          - 0x0033
> +          - 0x0039
>   
>         clocks:
> -        items:
> -          - description: Reference clock
> +        maxItems: 1

Can't this stay as is?

>   
>         clock-names:
>           items:
> @@ -142,8 +92,6 @@ patternProperties:
>         - device_type
>         - vendor-id
>         - device-id
> -      - clocks
> -      - clock-names

Any reason this was dropped here? I see in patch 14/16 you are still using 
clocks, clock-names for the PCIe port.

Thank you,
Claudiu

RE: [PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC

[John Madieu]

Hi Kryzstof,

Thanks for the feedback. 

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Thursday, January 15, 2026 2:49 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 05/16] dt-bindings: PCI: renesas,r9a08g045s33-pcie:
> Document RZ/G3E SoC
> 
> On Wed, Jan 14, 2026 at 04:33:26PM +0100, John Madieu wrote:
> > Extend the existing device tree bindings for Renesas RZ/G3S PCIe
> > controller to include support for the RZ/G3E
> > (renesas,r9a09g047e57-pcie) PCIe controller. The RZ/G3E PCIe
> > controller is similar to RZ/G3S but has some key
> > differences:
> >
> >  - Uses a different device ID
> >  - Supports PCIe Gen3 (8.0 GT/s) link speeds
> >  - Uses a different clock naming (clkpmu vs clkl1pm)
> >  - Has a different set of interrupts, interrupt ordering, and reset
> > signals
> >
> > Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >  .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 243
> > +++++++++++++-----
> >  1 file changed, 172 insertions(+), 71 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> > index d668782546a2..c68bc76af35d 100644
> > ---
> > a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yam
> > +++ l
> > @@ -10,85 +10,34 @@ maintainers:
> >    - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> >  description:
> > -  Renesas RZ/G3S PCIe host controller complies with PCIe Base
> > Specification
> > -  4.0 and supports up to 5 GT/s (Gen2).
> > +  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe  Base
> > + Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and  up
> > + to 8 GT/s (Gen3) for RZ/G3E.
> >
> >  properties:
> >    compatible:
> > -    const: renesas,r9a08g045-pcie # RZ/G3S
> > +    enum:
> > +      - renesas,r9a08g045-pcie # RZ/G3S
> > +      - renesas,r9a09g047-pcie # RZ/G3E
> >
> >    reg:
> >      maxItems: 1
> >
> > -  interrupts:
> > -    items:
> 
> Same review as already in the past for Renesas. Broadest constraints
> always stay here and list should share items.
> 
> > -      - description: System error interrupt
> > -      - description: System error on correctable error interrupt
> > -      - description: System error on non-fatal error interrupt
> > -      - description: System error on fatal error interrupt
> > -      - description: AXI error interrupt
> > -      - description: INTA interrupt
> > -      - description: INTB interrupt
> > -      - description: INTC interrupt
> > -      - description: INTD interrupt
> > -      - description: MSI interrupt
> > -      - description: Link bandwidth interrupt
> > -      - description: PME interrupt
> > -      - description: DMA interrupt
> > -      - description: PCIe event interrupt
> > -      - description: Message interrupt
> > -      - description: All interrupts
> > -
> > -  interrupt-names:
> > -    items:
> > -      - description: serr
> > -      - description: ser_cor
> > -      - description: serr_nonfatal
> > -      - description: serr_fatal
> > -      - description: axi_err
> > -      - description: inta
> > -      - description: intb
> > -      - description: intc
> > -      - description: intd
> > -      - description: msi
> > -      - description: link_bandwidth
> > -      - description: pm_pme
> > -      - description: dma
> > -      - description: pcie_evt
> > -      - description: msg
> > -      - description: all
> > +  interrupts: true
> > +
> > +  interrupt-names: true
> >
> >    interrupt-controller: true
> >
> >    clocks:
> > -    items:
> > -      - description: System clock
> > -      - description: PM control clock
> > +    maxItems: 2
> >
> >    clock-names:
> > -    items:
> > -      - description: aclk
> > -      - description: pm
> > -
> > -  resets:
> > -    items:
> > -      - description: AXI2PCIe Bridge reset
> > -      - description: Data link layer/transaction layer reset
> > -      - description: Transaction layer (ACLK domain) reset
> > -      - description: Transaction layer (PCLK domain) reset
> > -      - description: Physical layer reset
> > -      - description: Configuration register reset
> > -      - description: Configuration register reset
> > -
> > -  reset-names:
> > -    items:
> > -      - description: aresetn
> > -      - description: rst_b
> > -      - description: rst_gp_b
> > -      - description: rst_ps_b
> > -      - description: rst_rsm_b
> > -      - description: rst_cfg_b
> > -      - description: rst_load_b
> > +    maxItems: 2
> > +
> > +  resets: true
> > +
> > +  reset-names: true
> >
> >    power-domains:
> >      maxItems: 1
> > @@ -128,11 +77,12 @@ patternProperties:
> >          const: 0x1912
> >
> >        device-id:
> > -        const: 0x0033
> > +        enum:
> > +          - 0x0033
> > +          - 0x0039
> >
> >        clocks:
> > -        items:
> > -          - description: Reference clock
> > +        maxItems: 1
> >
> >        clock-names:
> >          items:
> > @@ -142,8 +92,6 @@ patternProperties:
> >        - device_type
> >        - vendor-id
> >        - device-id
> > -      - clocks
> > -      - clock-names
> >
> >      unevaluatedProperties: false
> >
> > @@ -167,6 +115,159 @@ required:
> >
> >  allOf:
> >    - $ref: /schemas/pci/pci-host-bridge.yaml#
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a08g045-pcie
> > +    then:
> > +      properties:
> > +        interrupts:
> > +          items:
> > +            - description: System error interrupt
> > +            - description: System error on correctable error interrupt
> > +            - description: System error on non-fatal error interrupt
> > +            - description: System error on fatal error interrupt
> > +            - description: AXI error interrupt
> > +            - description: INTA interrupt
> > +            - description: INTB interrupt
> > +            - description: INTC interrupt
> > +            - description: INTD interrupt
> > +            - description: MSI interrupt
> > +            - description: Link bandwidth interrupt
> > +            - description: PME interrupt
> > +            - description: DMA interrupt
> > +            - description: PCIe event interrupt
> > +            - description: Message interrupt
> > +            - description: All interrupts
> > +        interrupt-names:
> > +          items:
> > +            - const: serr
> 
> So serr is first...
> 
> > +            - const: serr_cor
> > +            - const: serr_nonfatal
> > +            - const: serr_fatal
> > +            - const: axi_err
> > +            - const: inta
> > +            - const: intb
> > +            - const: intc
> > +            - const: intd
> > +            - const: msi
> > +            - const: link_bandwidth
> > +            - const: pm_pme
> > +            - const: dma
> > +            - const: pcie_evt
> > +            - const: msg
> > +            - const: all
> > +        clocks:
> > +          items:
> > +            - description: System clock
> > +            - description: PM control clock
> > +        clock-names:
> > +          items:
> > +            - const: aclk
> > +            - const: pm
> > +        resets:
> > +          items:
> > +            - description: AXI2PCIe Bridge reset
> > +            - description: Data link layer/transaction layer reset
> > +            - description: Transaction layer (ACLK domain) reset
> > +            - description: Transaction layer (PCLK domain) reset
> > +            - description: Physical layer reset
> > +            - description: Configuration register reset
> > +            - description: Configuration register reset
> > +        reset-names:
> > +          items:
> > +            - const: aresetn
> > +            - const: rst_b
> > +            - const: rst_gp_b
> > +            - const: rst_ps_b
> > +            - const: rst_rsm_b
> > +            - const: rst_cfg_b
> > +            - const: rst_load_b
> > +      patternProperties:
> > +        "^pcie@0,[0-0]$":
> > +          properties:
> > +            device-id:
> > +              const: 0x0033
> > +          required:
> > +            - clocks
> > +            - clock-names
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g047-pcie
> > +    then:
> > +      properties:
> > +        interrupts:
> > +          items:
> > +            - description: All interrupts
> > +            - description: INTA interrupt
> > +            - description: INTB interrupt
> > +            - description: INTC interrupt
> > +            - description: INTD interrupt
> > +            - description: MSI interrupt
> > +            - description: Link bandwidth interrupt
> > +            - description: Link equalization request interrupt
> > +            - description: PME interrupt
> > +            - description: System error interrupt
> > +            - description: System error on correctable error interrupt
> > +            - description: System error on non-fatal error interrupt
> > +            - description: System error on fatal error interrupt
> > +            - description: DMA interrupt
> > +            - description: PCIe event interrupt
> > +            - description: AXI error interrupt
> > +            - description: Message interrupt
> > +            - description: Turn off event interrupt
> > +            - description: PMU power off interrupt
> > +            - description: D3 event function 0 interrupt
> > +            - description: D3 event function 1 interrupt
> > +            - description: Configuration PMCSR write clear function 0
> interrupt
> > +            - description: Configuration PMCSR write clear function 1
> interrupt
> > +        interrupt-names:
> > +          items:
> > +            - const: all
> > +            - const: inta
> > +            - const: intb
> > +            - const: intc
> > +            - const: intd
> > +            - const: msi
> > +            - const: link_bandwidth
> > +            - const: link_equalization_request
> > +            - const: pm_pme
> > +            - const: serr
> 
> And middle? What sort of mess is this?
> 
> Please learn from existing review, organize internal knowledge so we won't
> be repeating the same.
> 

I'll have a look at similar approaches and update for v2.

Regards,
John

> I am not reviewing the rest.
> 
> Best regards,
> Krzysztof

RE: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[John Madieu]

Hi Claudiu,

Thanks for the review.

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Thursday, January 15, 2026 2:13 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Cc: robh@kernel.org; bhelgaas@google.com; conor+dt@kernel.org; magnus.damm
> <magnus.damm@gmail.com>; Biju Das <biju.das.jz@bp.renesas.com>; linux-
> pci@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> john.madieu@gmail.com
> Subject: Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe
> error path
> 
> Hi, John,
> 
> On 1/14/26 17:33, John Madieu wrote:
> > Fix incorrect reset_control_bulk_deassert() call in the probe error
> > path. When unwinding from a failed pci_host_probe(), the configuration
> > resets should be asserted to restore the hardware to its initial
> > state, not deasserted again.
> >
> > Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host
> > driver")
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
> > b/drivers/pci/controller/pcie-rzg3s-host.c
> > index 5aa58638903f..c1053f95bc95 100644
> > --- a/drivers/pci/controller/pcie-rzg3s-host.c
> > +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> > @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct
> > platform_device *pdev)
> >
> >   host_probe_teardown:
> >   	rzg3s_pcie_teardown_irqdomain(host);
> > -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> > +	reset_control_bulk_assert(host->data->num_cfg_resets,
> >   				    host->cfg_resets);
> 
> This now fits on an 80 chars line, could you please update it like:
> 
> 	reset_control_bulk_assert(host->data->num_cfg_resets, host-
> >cfg_resets);
> 

It's precisely 81 chars in total, but for a better readability,
I'll do it your way in v2.

Regards,
John

> Thank you,
> Claudiu

Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Fix incorrect reset_control_bulk_deassert() call in the probe error
> path. When unwinding from a failed pci_host_probe(), the configuration
> resets should be asserted to restore the hardware to its initial state,
> not deasserted again.
> 
> Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver")

The title of the commit with SHA1 7ef502fb35b2 is "PCI: Add Renesas RZ/G3S host 
controller driver". With that addressed:

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 5aa58638903f..c1053f95bc95 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   
>   host_probe_teardown:
>   	rzg3s_pcie_teardown_irqdomain(host);
> -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> +	reset_control_bulk_assert(host->data->num_cfg_resets,
>   				    host->cfg_resets);
>   rpm_put:
>   	pm_runtime_put_sync(dev);

Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Fix incorrect reset_control_bulk_deassert() call in the probe error
> path. When unwinding from a failed pci_host_probe(), the configuration
> resets should be asserted to restore the hardware to its initial state,
> not deasserted again.
> 
> Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver")

The title of the commit with SHA1 7ef502fb35b2 is "PCI: Add Renesas RZ/G3S host 
controller driver".

> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 5aa58638903f..c1053f95bc95 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   
>   host_probe_teardown:
>   	rzg3s_pcie_teardown_irqdomain(host);
> -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> +	reset_control_bulk_assert(host->data->num_cfg_resets,
>   				    host->cfg_resets);
>   rpm_put:
>   	pm_runtime_put_sync(dev);

Re: [PATCH 02/16] PCI: rzg3s-host: Fix inbound window size tracking

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> The current implementation incorrectly resets size_id each iteration
> instead of accumulating, causing incorrect remaining size calculations
> when mapping DMA regions across multiple windows.
> 
> Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver")

Same here with regards to the commit title.

> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index c1053f95bc95..205b60421be1 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -1313,7 +1313,7 @@ static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,
>   
>   		pci_addr += size;
>   		cpu_addr += size;
> -		size_id = size;
> +		size_id += size;
>   		id++;
>   	}
>   	*index = id;

Re: [PATCH 06/16] PCI: rzg3s-host: Make SYSC register offsets SoC-specific

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> In preparation for adding RZ/G3E support, move the RST_RSM_B register
> offset and mask into a SoC-specific data structure. Compared with RZ/G3S,
> the RZ/G3E SYSC controls different functionalities for the PCIe controller.
> 
> Make SYSC operations conditional on the presence of register offset
> information, allowing the driver to handle SoCs that don't use the
> RST_RSM_B signal.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 93 +++++++++++++++++-------
>   1 file changed, 67 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 205b60421be1..44728771afa3 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -159,10 +159,6 @@
>   
>   #define RZG3S_PCI_CFG_PCIEC			0x60
>   
> -/* System controller registers */
> -#define RZG3S_SYS_PCIE_RST_RSM_B		0xd74
> -#define RZG3S_SYS_PCIE_RST_RSM_B_MASK		BIT(0)
> -
>   /* Maximum number of windows */
>   #define RZG3S_MAX_WINDOWS			8
>   
> @@ -174,6 +170,34 @@
>   /* Timeouts experimentally determined */
>   #define RZG3S_REQ_ISSUE_TIMEOUT_US		2500
>   
> +/**
> + * struct rzg3s_sysc_function - System Controller register function descriptor
> + * @offset: Register offset from the System Controller base address
> + * @mask: Bit mask for the function within the register
> + */
> +struct rzg3s_sysc_function {
> +	u32 offset;
> +	u32 mask;
> +};
> +
> +/**
> + * struct rzg3s_sysc_info - RZ/G3S System Controller function info
> + * @rst_rsm_b: Reset RSM_B function descriptor
> + */
> +struct rzg3s_sysc_info {
> +	struct rzg3s_sysc_function rst_rsm_b;
> +};
> +
> +/**
> + * struct rzg3s_sysc - RZ/G3S System Controller descriptor
> + * @regmap: System controller regmap
> + * @info: System controller info
> + */
> +struct rzg3s_sysc {
> +	struct regmap *regmap;
> +	const struct rzg3s_sysc_info *info;
> +};
> +
>   /**
>    * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
>    * @domain: IRQ domain
> @@ -203,6 +227,7 @@ struct rzg3s_pcie_host;
>    *                power-on
>    * @cfg_resets: array with the resets that need to be de-asserted after
>    *              configuration
> + * @sysc_info: SYSC functionalities
>    * @num_power_resets: number of power resets
>    * @num_cfg_resets: number of configuration resets
>    */
> @@ -210,6 +235,7 @@ struct rzg3s_pcie_soc_data {
>   	int (*init_phy)(struct rzg3s_pcie_host *host);
>   	const char * const *power_resets;
>   	const char * const *cfg_resets;
> +	struct rzg3s_sysc_info sysc_info;
>   	u8 num_power_resets;
>   	u8 num_cfg_resets;
>   };
> @@ -233,7 +259,7 @@ struct rzg3s_pcie_port {
>    * @dev: struct device
>    * @power_resets: reset control signals that should be set after power up
>    * @cfg_resets: reset control signals that should be set after configuration
> - * @sysc: SYSC regmap
> + * @sysc: SYSC descriptor
>    * @intx_domain: INTx IRQ domain
>    * @data: SoC specific data
>    * @msi: MSI data structure
> @@ -248,7 +274,7 @@ struct rzg3s_pcie_host {
>   	struct device *dev;
>   	struct reset_control_bulk_data *power_resets;
>   	struct reset_control_bulk_data *cfg_resets;
> -	struct regmap *sysc;
> +	struct rzg3s_sysc *sysc;
>   	struct irq_domain *intx_domain;
>   	const struct rzg3s_pcie_soc_data *data;
>   	struct rzg3s_pcie_msi msi;
> @@ -1516,6 +1542,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   	struct device_node *sysc_np __free(device_node) =
>   		of_parse_phandle(np, "renesas,sysc", 0);
>   	struct rzg3s_pcie_host *host;
> +	struct rzg3s_sysc *sysc;
>   	int ret;
>   
>   	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
> @@ -1527,6 +1554,13 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   	host->data = device_get_match_data(dev);
>   	platform_set_drvdata(pdev, host);
>   
> +	host->sysc = devm_kzalloc(dev, sizeof(*host->sysc), GFP_KERNEL);
> +	if (!host->sysc)
> +		return -ENOMEM;
> +
> +	sysc = host->sysc;
> +	sysc->info = &host->data->sysc_info;
> +
>   	host->axi = devm_platform_ioremap_resource(pdev, 0);
>   	if (IS_ERR(host->axi))
>   		return PTR_ERR(host->axi);
> @@ -1540,15 +1574,16 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   	if (ret)
>   		return ret;
>   
> -	host->sysc = syscon_node_to_regmap(sysc_np);
> -	if (IS_ERR(host->sysc)) {
> -		ret = PTR_ERR(host->sysc);
> +	sysc->regmap = syscon_node_to_regmap(sysc_np);
> +	if (IS_ERR(sysc->regmap)) {
> +		ret = PTR_ERR(sysc->regmap);
>   		goto port_refclk_put;
>   	}
>   
> -	ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
> -				 RZG3S_SYS_PCIE_RST_RSM_B_MASK,
> -				 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
> +	ret = regmap_update_bits(sysc->regmap,
> +				 sysc->info->rst_rsm_b.offset,

This can stay on the previous line to spare one extra line of code.

The rest LGTM.

Thank you,
Claudiu

Re: [PATCH 07/16] PCI: rzg3s-host: Make configuration reset lines optional

[Claudiu Beznea]

On 1/14/26 17:33, John Madieu wrote:
> Some SoC variants such as RZ/G3E handles configuration reset control
> through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets
> optional by using devm_reset_control_bulk_get_optional_exclusive() to allow
> SoCs to use alternative or complementaty reset control mechanisms.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 44728771afa3..fcedccadecf6 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -1161,9 +1161,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)
>   	if (ret)
>   		return ret;
>   
> -	return devm_reset_control_bulk_get_exclusive(host->dev,
> -						     data->num_cfg_resets,
> -						     host->cfg_resets);
> +	return devm_reset_control_bulk_get_optional_exclusive(host->dev,
> +							      data->num_cfg_resets,
> +							      host->cfg_resets);
>   }
>   
>   static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)

Re: [PATCH 08/16] PCI: rzg3s-host: Make inbound window setup SoC-specific

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Different RZ/G3 SoCs have different requirements for inbound window
> configuration. While both require power-of-2 sized windows (4KB * 2^N),
> they differ in how non-power-of-2 memory regions are handled:

AFAICT, both RZ/G3S and RZ/G3E HW manuals document the setup of the inbound 
windows the same. Please point me to the proper chapter in case I'm wrong.

Moreover, I tested the code from rzg3e_pcie_set_inbound_windows() (proposed in 
patch 12/16) to setup the inbound window on RZ/G3S and I see no differences in 
terms of mapped regions and functionality. So, unless I'm missing something, I 
think better to use the same code for window setup.

Thank you,
Claudiu

> 
> - RZ/G3S: Uses roundup_pow_of_two() to create a single larger window
>    that may over-map beyond the actual memory region. This approach is
>    simpler but relies on hardware tolerance for over-mapped regions.
> 
> - RZ/G3E: Requires precise coverage without over-mapping. Memory regions
>    must be split into multiple power-of-2 windows, and window sizes must
>    respect address alignment constraints to ensure proper hardware address
>    decoding.
> 
> Move the inbound window sizing and splitting logic to a SoC-specific
> callback to accommodate these differences. This allows each SoC variant
> to implement its own window setup strategy while maintaining the common
> window programming sequence.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index fcedccadecf6..a9773e5f25c7 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -223,6 +223,7 @@ struct rzg3s_pcie_host;
>   /**
>    * struct rzg3s_pcie_soc_data - SoC specific data
>    * @init_phy: PHY initialization function
> + * @set_inbound_windows: SoC-specific function to set up inbound windows
>    * @power_resets: array with the resets that need to be de-asserted after
>    *                power-on
>    * @cfg_resets: array with the resets that need to be de-asserted after
> @@ -233,6 +234,9 @@ struct rzg3s_pcie_host;
>    */
>   struct rzg3s_pcie_soc_data {
>   	int (*init_phy)(struct rzg3s_pcie_host *host);
> +	int (*set_inbound_windows)(struct rzg3s_pcie_host *host,
> +				   struct resource_entry *entry,
> +				   int *index);
>   	const char * const *power_resets;
>   	const char * const *cfg_resets;
>   	struct rzg3s_sysc_info sysc_info;
> @@ -1354,7 +1358,7 @@ static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host)
>   	int i = 0, ret;
>   
>   	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> -		ret = rzg3s_pcie_set_inbound_windows(host, entry, &i);
> +		ret = host->data->set_inbound_windows(host, entry, &i);
>   		if (ret)
>   			return ret;
>   	}
> @@ -1753,6 +1757,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
>   	.cfg_resets = rzg3s_soc_cfg_resets,
>   	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
>   	.init_phy = rzg3s_soc_pcie_init_phy,
> +	.set_inbound_windows = rzg3s_pcie_set_inbound_windows,
>   	.sysc_info = {
>   		.rst_rsm_b = {
>   			.offset = 0xd74,

Re: [PATCH 09/16] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks
> to handle SoC-specific configuration methods. While RZ/G3S uses the Linux
> reset framework with dedicated reset lines, other SoC variants like RZ/G3E
> control configuration resets through PCIe AXI registers.
> 
> As Linux reset bulk API gracefully handles optional NULL reset lines
> (num_cfg_resets = 0 for RZ/G3E), the driver continues to use the standard
> reset framework when reset lines are available, while custom callbacks
> are only invoked when provided.
> 
> This provides a balanced pattern where:
> - RZ/G3S: Uses reset framework only, no callbacks needed
> - RZ/G3E: Sets num_cfg_resets=0, provides cfg_pre_init/cfg_post_init/cfg_deinit
> - In addition to that, RZ/G3E requires explicit cfg reset and clok turned off
>    to put the PCIe IP in a known state.
> 
> Add cfg_pre_init, cfg_post_init, and cfg_deinit callbacks to support
> custom configuration mechanism in preparation to RZ/G3E PCIe support.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 54 ++++++++++++++++++------
>   1 file changed, 40 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index a9773e5f25c7..bb071bacd0b2 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -224,6 +224,9 @@ struct rzg3s_pcie_host;
>    * struct rzg3s_pcie_soc_data - SoC specific data
>    * @init_phy: PHY initialization function
>    * @set_inbound_windows: SoC-specific function to set up inbound windows
> + * @cfg_pre_init: Optional callback for SoC-specific pre-configuration
> + * @cfg_post_init: Optional callback for SoC-specific post-configuration
> + * @cfg_deinit: Optional callback for SoC-specific de-initialization
>    * @power_resets: array with the resets that need to be de-asserted after
>    *                power-on
>    * @cfg_resets: array with the resets that need to be de-asserted after
> @@ -237,6 +240,9 @@ struct rzg3s_pcie_soc_data {
>   	int (*set_inbound_windows)(struct rzg3s_pcie_host *host,
>   				   struct resource_entry *entry,
>   				   int *index);
> +	void (*cfg_pre_init)(struct rzg3s_pcie_host *host);
> +	int (*cfg_post_init)(struct rzg3s_pcie_host *host);
> +	void (*cfg_deinit)(struct rzg3s_pcie_host *host);

Looking on patch 12/16, I see you have rzg3e_pcie_config_pre_init(). I think it 
make sense to name these:

- config_pre_init
- config_post_init
- config_deinit

As all these are related to the setting done for the config unit (CFGU) and 
there is already rzg3s_pcie_config_init() function taking care of this.

>   	const char * const *power_resets;
>   	const char * const *cfg_resets;
>   	struct rzg3s_sysc_info sysc_info;
> @@ -1119,6 +1125,12 @@ static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host)
>   	writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS);
>   }
>   
> +static int rzg3s_cfg_post_init(struct rzg3s_pcie_host *host)

Based on the above mentioned rationale, please rename it 
rzg3s_config_post_init() and move it close to rzg3s_pcie_config_init().

> +{
> +	return reset_control_bulk_deassert(host->data->num_cfg_resets,
> +					   host->cfg_resets);
> +}
> +
>   static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host)
>   {
>   	const struct rzg3s_pcie_soc_data *data = host->data;
> @@ -1233,6 +1245,10 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
>   	u32 val;
>   	int ret;
>   
> +	/* SoC-specific pre-configuration */
> +	if (host->data->cfg_pre_init)
> +		host->data->cfg_pre_init(host);
> +

In pre_init() from patch 12/16 the code de-asserts LOAD_B and CFG_B. I think 
those should be asserted back in failure path of rzg3s_pcie_config_init(), 
rzg3s_pcie_host_init_port(), host->data->cfg_post_init(). Jumping to cfg_deinit 
label would to the work for now.

>   	/* Initialize the PCIe related registers */
>   	ret = rzg3s_pcie_config_init(host);
>   	if (ret)
> @@ -1245,8 +1261,8 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
>   	/* Initialize the interrupts */
>   	rzg3s_pcie_irq_init(host);
>   
> -	ret = reset_control_bulk_deassert(host->data->num_cfg_resets,
> -					  host->cfg_resets);
> +	/* SoC-specific post-configuration */
> +	ret = host->data->cfg_post_init(host);
>   	if (ret)
>   		goto disable_port_refclk;
>   
> @@ -1257,14 +1273,17 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
>   				 PCIE_LINK_WAIT_SLEEP_MS * MILLI *
>   				 PCIE_LINK_WAIT_MAX_RETRIES);
>   	if (ret)
> -		goto cfg_resets_deassert;
> +		goto cfg_deinit;
>   
>   	val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
>   	dev_info(host->dev, "PCIe link status [0x%x]\n", val);
>   
>   	return 0;
>   
> -cfg_resets_deassert:
> +cfg_deinit:
> +	if (host->data->cfg_deinit)
> +		host->data->cfg_deinit(host);
> +
>   	reset_control_bulk_assert(host->data->num_cfg_resets,
>   				  host->cfg_resets);

It looks to me that you can also implement deinit for RZ/G3S that will only call:

    	reset_control_bulk_assert(host->data->num_cfg_resets,
    				  host->cfg_resets);

With that, the resulting code should be simpler.

Otherwise, you will have to also call deinit() on the probe, suspend/resume 
failure path, close to reset_control_bulk_assert() for cfg resets.


>   disable_port_refclk:
> @@ -1609,6 +1628,9 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   	if (ret)
>   		goto rpm_disable;
>   
> +	if (host->data->cfg_deinit)
> +		host->data->cfg_deinit(host);
> +

Can we keep this before host->data->cfg_pre_init() call from 
rzg3s_pcie_host_init() ? Or, embed it in cfg_pre_init() implementation for RZ/G3E ?

In Table 6.6-130 Initialization Procedure (RC) from the RZ/G3E HW manual, the 
steps are one after each other.

Doing it like this will drop the necessity to update rzg3s_pcie_probe().

>   	raw_spin_lock_init(&host->hw_lock);
>   
>   	ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain,
> @@ -1663,32 +1685,35 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
>   
>   	clk_disable_unprepare(port->refclk);
>   
> -	ret = reset_control_bulk_assert(data->num_power_resets,
> -					host->power_resets);
> -	if (ret)
> -		goto refclk_restore;
> +	/* SoC-specific de-initialization */
> +	if (data->cfg_deinit)
> +		data->cfg_deinit(host);
>   
>   	ret = reset_control_bulk_assert(data->num_cfg_resets,
>   					host->cfg_resets);
>   	if (ret)

With deinit() for RZ/G3S calling reset_control_bulk_assert() you will have only:

if (data->cfg_deinit)
     data->cfg_deinit();

here. Also, take into account that reset control assert/de-assert can return 
errors. So, your APIs will have to be modeled with this in mind.


> -		goto power_resets_restore;

> +		goto cfg_reinit;

Jumping to cfg_reinit label is not actually right, for RZ/G3S at least. The 
reset_control_bulk_assert() function take care the resets passed as arguments 
are de-asserted back in case of failure. The code here jumps to cfg_reinit() 
which for the RZ/G3S SoC just calls again de-assert for the cfg resets.

> +
> +	ret = reset_control_bulk_assert(data->num_power_resets,
> +					host->power_resets);
> +	if (ret)
> +		goto cfg_reinit;

You changed the order here. I get it why, but it should have been done and 
explained, in a separate patch.

Thank you,
Claudiu

>   
>   	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
>   				 sysc->info->rst_rsm_b.mask,
>   				 field_prep(sysc->info->rst_rsm_b.mask, 0));
>   	if (ret)
> -		goto cfg_resets_restore;
> +		goto power_resets_restore;
>   
>   	return 0;
>   
>   	/* Restore the previous state if any error happens */
> -cfg_resets_restore:
> -	reset_control_bulk_deassert(data->num_cfg_resets,
> -				    host->cfg_resets);
>   power_resets_restore:
>   	reset_control_bulk_deassert(data->num_power_resets,
>   				    host->power_resets);
> -refclk_restore:
> +cfg_reinit:
> +	data->cfg_post_init(host);
> +
>   	clk_prepare_enable(port->refclk);
>   	pm_runtime_resume_and_get(dev);
>   	return ret;
> @@ -1756,6 +1781,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
>   	.num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets),
>   	.cfg_resets = rzg3s_soc_cfg_resets,
>   	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
> +	.cfg_post_init = rzg3s_cfg_post_init,
>   	.init_phy = rzg3s_soc_pcie_init_phy,
>   	.set_inbound_windows = rzg3s_pcie_set_inbound_windows,
>   	.sysc_info = {

Re: [PATCH 11/16] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support

[Claudiu Beznea]

On 1/14/26 17:33, John Madieu wrote:
> Extend the link speed configuration to support Gen3 (8.0 GT/s) in addition
> to Gen2 (5.0 GT/s). This is required for RZ/G3E PCIe host support, which is
> Gen3 capable.
> 
> Instead of relying on DT max-link-speed for configuration, read the hardware
> capabilities from the PCI_EXP_LNKCAP register to determine the maximum
> supported speed. The DT max-link-speed property is now only used as an
> optional limit when explicitly specified, which aligns with PCIe subsystem
> expectations.
> 
> Signed-off-by: John Madieu<john.madieu.xa@bp.renesas.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Re: [PATCH 12/16] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller

[Claudiu Beznea]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Add support for the PCIe controller found in RZ/G3E SoCs to the existing
> RZ/G3S PCIe host driver. The RZ/G3E PCIe controller is similar to the
> RZ/G3S's, with the following key differences:
> 
>   - Supports PCIe Gen3 (8.0 GT/s) link speeds alongside Gen2 (5.0 GT/s)
>   - Uses a different reset control mechanism via AXI registers instead
>     of the Linux reset framework
>   - Requires specific SYSC configuration for link state control and
>     Root Complex mode selection
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 231 ++++++++++++++++++++---
>   1 file changed, 209 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index b0a5c08d2527..b046360e92da 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -111,6 +111,16 @@
>   #define RZG3S_PCI_PERM_CFG_HWINIT_EN		BIT(2)
>   #define RZG3S_PCI_PERM_PIPE_PHY_REG_EN		BIT(1)
>   
> +/* RZ/G3E specific registers */
> +#define RZG3E_PCI_RESET				0x310
> +#define RZG3E_PCI_RESET_RST_OUT_B		BIT(6)
> +#define RZG3E_PCI_RESET_RST_PS_B		BIT(5)
> +#define RZG3E_PCI_RESET_RST_LOAD_B		BIT(4)
> +#define RZG3E_PCI_RESET_RST_CFG_B		BIT(3)
> +#define RZG3E_PCI_RESET_RST_RSM_B		BIT(2)
> +#define RZG3E_PCI_RESET_RST_GP_B		BIT(1)
> +#define RZG3E_PCI_RESET_RST_B			BIT(0)
> +
>   #define RZG3S_PCI_MSIRE(id)			(0x600 + (id) * 0x10)
>   #define RZG3S_PCI_MSIRE_ENA			BIT(0)
>   
> @@ -183,9 +193,13 @@ struct rzg3s_sysc_function {
>   /**
>    * struct rzg3s_sysc_info - RZ/G3S System Controller function info
>    * @rst_rsm_b: Reset RSM_B function descriptor
> + * @l1_allow: L1 power state management function descriptor
> + * @mode: Mode configuration function descriptor
>    */
>   struct rzg3s_sysc_info {
>   	struct rzg3s_sysc_function rst_rsm_b;
> +	struct rzg3s_sysc_function l1_allow;
> +	struct rzg3s_sysc_function mode;
>   };
>   
>   /**
> @@ -1201,6 +1215,10 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)
>   	if (ret)
>   		return ret;
>   
> +	/* Mandatory for RZ/G3E, harmless for RZ/G3S */
> +	reset_control_bulk_assert(data->num_power_resets,
> +				  host->power_resets);
> +

This is similar to what the IP needs for clock when the mode is changed (RC or 
EP). Could it be handled in a similar way the clocks were handled (make sure it 
is asserted on the reset driver probe)?

>   	return devm_reset_control_bulk_get_optional_exclusive(host->dev,
>   							      data->num_cfg_resets,
>   							      host->cfg_resets);
> @@ -1266,6 +1284,7 @@ static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host)
>   
>   static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
>   {
> +	const struct rzg3s_sysc_info *sysc_info = host->sysc->info;
>   	u32 val;
>   	int ret;
>   
> @@ -1282,6 +1301,16 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
>   	if (ret)
>   		return ret;
>   
> +	/* Enable ASPM L1 transition for SoCs that use it */
> +	if (sysc_info->l1_allow.mask) {
> +		ret = regmap_update_bits(host->sysc->regmap,
> +					 sysc_info->l1_allow.offset,
> +					 sysc_info->l1_allow.mask,
> +					 field_prep(sysc_info->l1_allow.mask, 1));
> +		if (ret)

Should the code jump to cfg_deinit label to de-assert some of the resets 
asserted though cfg_pre_init() ?

> +			return ret;
> +	}
> +
>   	/* Initialize the interrupts */
>   	rzg3s_pcie_irq_init(host);
>   
> @@ -1625,12 +1654,27 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   		goto port_refclk_put;
>   	}
>   
> -	ret = regmap_update_bits(sysc->regmap,
> -				 sysc->info->rst_rsm_b.offset,
> -				 sysc->info->rst_rsm_b.mask,
> -				 field_prep(sysc->info->rst_rsm_b.mask, 1));
> -	if (ret)
> -		goto port_refclk_put;
> +	/*
> +	 * Put controller in RC (Root Complex) mode for SoCs that
> +	 * support it. These can operate in either EP or RC mode.
> +	 */
> +	if (sysc->info->mode.mask) {
> +		ret = regmap_write(sysc->regmap,
> +				   sysc->info->mode.offset,

This can go on the previous line to save one line of code.

> +				   sysc->info->mode.mask);
> +		if (ret)
> +			goto port_refclk_put;
> +	}
> +
> +	/* De-assert SYSC RST_RSM_B only if used by the SoC */

This comment wasn't here previously. I don't think it is not needed, FMPOV.

> +	if (sysc->info->rst_rsm_b.mask) {
> +		ret = regmap_update_bits(sysc->regmap,
> +					 sysc->info->rst_rsm_b.offset,
> +					 sysc->info->rst_rsm_b.mask,
> +					 field_prep(sysc->info->rst_rsm_b.mask, 1));
> +		if (ret)
> +			goto port_refclk_put;
> +	}
>   
>   	ret = rzg3s_pcie_resets_prepare_and_get(host);
>   	if (ret)
> @@ -1684,9 +1728,11 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
>   	 * SYSC RST_RSM_B signal need to be asserted before turning off the
>   	 * power to the PHY.
>   	 */
> -	regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
> -			   sysc->info->rst_rsm_b.mask,
> -			   field_prep(sysc->info->rst_rsm_b.mask, 0));
> +	if (sysc->info->rst_rsm_b.mask)

This driver is using (almost everywhere) { } on code blocks spanning multiple 
lines even though they represent a single function call like in this case. For 
consistency, I would use the same principle.

> +		regmap_update_bits(sysc->regmap,
> +				   sysc->info->rst_rsm_b.offset,
> +				   sysc->info->rst_rsm_b.mask,
> +				   field_prep(sysc->info->rst_rsm_b.mask, 0));
>   port_refclk_put:
>   	clk_put(host->port.refclk);
>   
> @@ -1721,11 +1767,15 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
>   	if (ret)
>   		goto cfg_reinit;
>   
> -	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
> -				 sysc->info->rst_rsm_b.mask,
> -				 field_prep(sysc->info->rst_rsm_b.mask, 0));
> -	if (ret)
> -		goto power_resets_restore;
> +	/* Assert SYSC RST_RSM_B if supported */

Comment was not there previously. Could you please drop it?

> +	if (sysc->info->rst_rsm_b.mask) {
> +		ret = regmap_update_bits(sysc->regmap,
> +					 sysc->info->rst_rsm_b.offset,
> +					 sysc->info->rst_rsm_b.mask,
> +					 field_prep(sysc->info->rst_rsm_b.mask, 0));
> +		if (ret)
> +			goto power_resets_restore;
> +	}
>   
>   	return 0;
>   
> @@ -1748,11 +1798,23 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)
>   	struct rzg3s_sysc *sysc = host->sysc;
>   	int ret;
>   
> -	ret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
> -				 sysc->info->rst_rsm_b.mask,
> -				 field_prep(sysc->info->rst_rsm_b.mask, 1));
> -	if (ret)
> -		return ret;
> +	/* De-assert SYSC RST_RSM_B if supported */
> +	if (sysc->info->rst_rsm_b.mask) {
> +		ret = regmap_update_bits(sysc->regmap,
> +					 sysc->info->rst_rsm_b.offset,
> +					 sysc->info->rst_rsm_b.mask,
> +					 field_prep(sysc->info->rst_rsm_b.mask, 1));
> +		if (ret)
> +			return ret;
> +	}
> +
> +	if (sysc->info->mode.mask) {
> +		ret = regmap_write(sysc->regmap,
> +				   sysc->info->mode.offset,
> +				   sysc->info->mode.mask);
> +		if (ret)
> +			return ret;
> +	}

Could you please keep the same order as in probe:
1/ set mode
2/ set rst_rsm_b

?

>   
>   	ret = rzg3s_pcie_power_resets_deassert(host);
>   	if (ret)
> @@ -1779,12 +1841,133 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)
>   	reset_control_bulk_assert(data->num_power_resets,
>   				  host->power_resets);
>   assert_rst_rsm_b:
> -	regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,
> -			   sysc->info->rst_rsm_b.mask,
> -			   field_prep(sysc->info->rst_rsm_b.mask, 0));
> +	if (sysc->info->rst_rsm_b.mask)

Multi line statement here as well, I would use { } around this block based on 
the rationale provided above.

> +		regmap_update_bits(sysc->regmap,
> +				   sysc->info->rst_rsm_b.offset,
> +				   sysc->info->rst_rsm_b.mask,
> +				   field_prep(sysc->info->rst_rsm_b.mask, 0));
>   	return ret;
>   }
>   
> +/* RZ/G3E SoC-specific implementations */
> +static void rzg3e_pcie_config_pre_init(struct rzg3s_pcie_host *host)
> +{
> +	/*
> +	 * De-assert LOAD_B and CFG_B during configuration phase.
> +	 * These are part of the RZ/G3E reset register, not reset framework.
> +	 * Other reset bits remain asserted until cfg_post_init.
> +	 */
> +	rzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,
> +			       RZG3E_PCI_RESET_RST_LOAD_B | RZG3E_PCI_RESET_RST_CFG_B,
> +			       RZG3E_PCI_RESET_RST_LOAD_B | RZG3E_PCI_RESET_RST_CFG_B);
> +}
> +
> +static void rzg3e_cfg_deinit(struct rzg3s_pcie_host *host)
> +{
> +	writel_relaxed(0, host->axi + RZG3E_PCI_RESET);
> +}
> +
> +static int rzg3e_cfg_post_init(struct rzg3s_pcie_host *host)
> +{
> +	/* De-assert PS_B, GP_B, RST_B */
> +	rzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,
> +			       RZG3E_PCI_RESET_RST_PS_B | RZG3E_PCI_RESET_RST_GP_B |
> +			       RZG3E_PCI_RESET_RST_B,
> +			       RZG3E_PCI_RESET_RST_PS_B | RZG3E_PCI_RESET_RST_GP_B |
> +			       RZG3E_PCI_RESET_RST_B);
> +
> +	/* Hardware requires >= 500us delay before final reset deassert */

Could you please cite the RZ/G3E HW manual chapter and revision, requiring this?

> +	fsleep(500);
> +
> +	/* De-assert OUT_B and RSM_B to complete reset sequence */
> +	rzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,
> +			       RZG3E_PCI_RESET_RST_OUT_B | RZG3E_PCI_RESET_RST_RSM_B,
> +			       RZG3E_PCI_RESET_RST_OUT_B | RZG3E_PCI_RESET_RST_RSM_B);
> +
> +	return 0;
> +}

Could you please move these config related function close to the other config 
specific functions?

> +
> +static int rzg3e_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,
> +					  struct resource_entry *entry,
> +					  int *index)

As mentioned in a previous patch, this works for RZ/G3E as well and I see no 
differences in HW manual b/w RZ/G3S and RZ/G3E, unless I'm missing something. 
Please use a single function for inbound setup if there is no restriction.

> +{
> +	u64 pci_addr = entry->res->start - entry->offset;
> +	u64 cpu_addr = entry->res->start;
> +	u64 cpu_end = entry->res->end;
> +	int id = *index;
> +	u64 size;
> +
> +	/*
> +	 * The RZ/G3E requires power-of-2 sizes (4K * 2^N) due to mask register
> +	 * format. Split non-power-of-2 regions into multiple windows to avoid
> +	 * over-mapping.
> +	 */
> +	while (cpu_addr <= cpu_end) {
> +		u64 remaining_size = cpu_end - cpu_addr + 1;
> +		u64 align_limit;
> +
> +		if (id >= RZG3S_MAX_WINDOWS)
> +			return dev_err_probe(host->dev, -ENOSPC,
> +					     "Failed to map inbound window for resource (%s)\n",
> +					     entry->res->name);
> +
> +		/* Start with largest power-of-two that fits in remaining size */
> +		size = 1ULL << __fls(remaining_size);
> +
> +		/*
> +		 * Find alignment limit - the largest power-of-two that both
> +		 * addresses are aligned to
> +		 */
> +		align_limit = min(cpu_addr ? (1ULL << __ffs(cpu_addr)) : ~0ULL,
> +				  pci_addr ? (1ULL << __ffs(pci_addr)) : ~0ULL);
> +
> +		/* Window size cannot exceed alignment */
> +		size = min(size, align_limit);
> +
> +		/*
> +		 * According to the RZ/G3E HW manual Rev.1.15,
> +		 * (Section 6.6.4.1.3.(74) AXI Window Mask (Lower) Register):
> +		 * The area which can be set is 4K * 2^N bytes.
> +		 */
> +		size = max(size, SZ_4K);
> +
> +		/*
> +		 * HW expects size - 1 for mask register.
> +		 * For example: 4KB (0x1000) becomes mask 0xfff (12 bits set).
> +		 */
> +		rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr,
> +					      size - 1, id);
> +
> +		cpu_addr += size;
> +		pci_addr += size;
> +		id++;
> +	}
> +	*index = id;
> +
> +	return 0;
> +}
> +
> +static const char * const rzg3e_soc_power_resets[] = { "aresetn" };
> +
> +static const struct rzg3s_pcie_soc_data rzg3e_soc_data = {

Could you please move rzg3e_soc_power_resets[] and rzg3e_soc_data after 
rzg3s_pcie_pm_ops to have all the RZ/G3E SoC specific data close to the RZ/G3S 
SoC specific data?

Thank you,
Claudiu

> +	.power_resets = rzg3e_soc_power_resets,
> +	.num_power_resets = ARRAY_SIZE(rzg3e_soc_power_resets),
> +	.cfg_post_init = rzg3e_cfg_post_init,
> +	.cfg_deinit = rzg3e_cfg_deinit,
> +	.cfg_pre_init = rzg3e_pcie_config_pre_init,
> +	.set_inbound_windows = rzg3e_pcie_set_inbound_windows,
> +	.sysc_info = {
> +		.l1_allow = {
> +			.offset = 0x1020,
> +			.mask = BIT(0),
> +		},
> +		.mode = {
> +			.offset = 0x1024,
> +			.mask = BIT(0),
> +		},
> +	},
> +};
> +
>   static const struct dev_pm_ops rzg3s_pcie_pm_ops = {
>   	NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq,
>   				  rzg3s_pcie_resume_noirq)
> @@ -1819,6 +2002,10 @@ static const struct of_device_id rzg3s_pcie_of_match[] = {
>   		.compatible = "renesas,r9a08g045-pcie",
>   		.data = &rzg3s_soc_data,
>   	},
> +	{
> +		.compatible = "renesas,r9a09g047-pcie",
> +		.data = &rzg3e_soc_data,
> +	},
>   	{}
>   };
>   

Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[Geert Uytterhoeven]

Hi John,

On Wed, 14 Jan 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Some peripherals may be left enabled by the bootloader but should be
> explicitly disabled by the kernel to ensure a known initial state.
> This is particularly important for PCIe which requires proper
> initialization sequencing.
>
> Add new macros DEF_MOD_INIT_OFF() to declare module clocks that should be
> turned off during CPG probe if found in the opposite state.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

However, I am still wondering if there are any possible bad side effects
of disabling the PCIe clocks, e.g. when PCIe is in use (network card,
SATA card, ...)?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/16] clk: renesas: r9a09g047: Add PCIe clocks and reset

[Geert Uytterhoeven]

Hi John,

On Wed, 14 Jan 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Add necessary clocks and reset entries for the PCIe controller
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -438,6 +438,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(3, BIT(4))),
>         DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
>                                                 BUS_MSTOP(2, BIT(15))),
> +       DEF_MOD_INIT_OFF("pcie_aclk",           CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,

"pcie_0_aclk", to match the documentation.

> +                                               BUS_MSTOP(1, BIT(15))),
> +       DEF_MOD_INIT_OFF("pcie_clk_pmu",        CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,

"pcie_0_clk_pmu"

> +                                               BUS_MSTOP(1, BIT(15))),

Do you need pcie_refclk_in and pcie_coreclkin?
Especially the latter seems to be document sparsely.

>  };
>
>  static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
> @@ -503,6 +507,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
>         DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
>         DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
>         DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
> +       DEF_RST(11, 2, 5, 3),           /* PCIE_ARESETN */

PCIE_0_ARESETN

>         DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
>         DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
>         DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 04/16] clk: renesas: r9a09g047: Add PCIe clocks and reset

[John Madieu]

Hi Geert,

Thanks for your review.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, January 20, 2026 12:03 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 04/16] clk: renesas: r9a09g047: Add PCIe clocks and
> reset
> 
> Hi John,
> 
> On Wed, 14 Jan 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Add necessary clocks and reset entries for the PCIe controller
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > @@ -438,6 +438,10 @@ static const struct rzv2h_mod_clk
> r9a09g047_mod_clks[] __initconst = {
> >                                                 BUS_MSTOP(3, BIT(4))),
> >         DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8,
> 10,
> >                                                 BUS_MSTOP(2,
> > BIT(15))),
> > +       DEF_MOD_INIT_OFF("pcie_aclk",           CLK_PLLDTY_ACPU_DIV2,
> 12, 4, 6, 4,
> 
> "pcie_0_aclk", to match the documentation.

Noted for v2.

> 
> > +                                               BUS_MSTOP(1, BIT(15))),
> > +       DEF_MOD_INIT_OFF("pcie_clk_pmu",        CLK_PLLDTY_ACPU_DIV2,
> 12, 5, 6, 5,
> 
> "pcie_0_clk_pmu"

Noted.

> 
> > +                                               BUS_MSTOP(1,
> > + BIT(15))),
> 
> Do you need pcie_refclk_in and pcie_coreclkin?
> Especially the latter seems to be document sparsely.
> 

These clocks are not needed. They were documented by mistake.

> >  };
> >
> >  static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@
> > -503,6 +507,7 @@ static const struct rzv2h_reset r9a09g047_resets[]
> __initconst = {
> >         DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
> >         DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
> >         DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
> > +       DEF_RST(11, 2, 5, 3),           /* PCIE_ARESETN */
> 
> PCIE_0_ARESETN

Noted.

Regards,
John

> 
> >         DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
> >         DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
> >         DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

RE: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[John Madieu]

Hi Geert,

Thanks for the review.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, January 20, 2026 11:50 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> init_off clocks
> 
> Hi John,
> 
> On Wed, 14 Jan 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Some peripherals may be left enabled by the bootloader but should be
> > explicitly disabled by the kernel to ensure a known initial state.
> > This is particularly important for PCIe which requires proper
> > initialization sequencing.
> >
> > Add new macros DEF_MOD_INIT_OFF() to declare module clocks that should
> > be turned off during CPG probe if found in the opposite state.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> Thanks for your patch!
> 
> LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> However, I am still wondering if there are any possible bad side effects
> of disabling the PCIe clocks, e.g. when PCIe is in use (network card, SATA
> card, ...)?

I'll test and let you know.

Regards,
John

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

RE: [PATCH 08/16] PCI: rzg3s-host: Make inbound window setup SoC-specific

[John Madieu]

Hi Claudiu,
Thanks for the review.

> -----Original Message-----
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Sent: Monday, January 19, 2026 7:15 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org


> Subject: Re: [PATCH 08/16] PCI: rzg3s-host: Make inbound window setup SoC-
> specific
> 
> Hi, John,
> 
> On 1/14/26 17:33, John Madieu wrote:
> > Different RZ/G3 SoCs have different requirements for inbound window
> > configuration. While both require power-of-2 sized windows (4KB *
> > 2^N), they differ in how non-power-of-2 memory regions are handled:
> 
> AFAICT, both RZ/G3S and RZ/G3E HW manuals document the setup of the
> inbound windows the same. Please point me to the proper chapter in case
> I'm wrong.
> 
> Moreover, I tested the code from rzg3e_pcie_set_inbound_windows()
> (proposed in patch 12/16) to setup the inbound window on RZ/G3S and I see
> no differences in terms of mapped regions and functionality. So, unless
> I'm missing something, I think better to use the same code for window
> setup.

Indeed, the RZ/G3E variant works with both SoCs. I'll keep that
single implementation for v2.

Regards,
John

> 
> Thank you,
> Claudiu
> 
> >
> > - RZ/G3S: Uses roundup_pow_of_two() to create a single larger window
> >    that may over-map beyond the actual memory region. This approach is
> >    simpler but relies on hardware tolerance for over-mapped regions.
> >
> > - RZ/G3E: Requires precise coverage without over-mapping. Memory regions
> >    must be split into multiple power-of-2 windows, and window sizes must
> >    respect address alignment constraints to ensure proper hardware
> address
> >    decoding.
> >
> > Move the inbound window sizing and splitting logic to a SoC-specific
> > callback to accommodate these differences. This allows each SoC
> > variant to implement its own window setup strategy while maintaining
> > the common window programming sequence.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >   drivers/pci/controller/pcie-rzg3s-host.c | 7 ++++++-
> >   1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
> > b/drivers/pci/controller/pcie-rzg3s-host.c
> > index fcedccadecf6..a9773e5f25c7 100644
> > --- a/drivers/pci/controller/pcie-rzg3s-host.c
> > +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> > @@ -223,6 +223,7 @@ struct rzg3s_pcie_host;
> >   /**
> >    * struct rzg3s_pcie_soc_data - SoC specific data
> >    * @init_phy: PHY initialization function
> > + * @set_inbound_windows: SoC-specific function to set up inbound
> > + windows
> >    * @power_resets: array with the resets that need to be de-asserted
> after
> >    *                power-on
> >    * @cfg_resets: array with the resets that need to be de-asserted
> > after @@ -233,6 +234,9 @@ struct rzg3s_pcie_host;
> >    */
> >   struct rzg3s_pcie_soc_data {
> >   	int (*init_phy)(struct rzg3s_pcie_host *host);
> > +	int (*set_inbound_windows)(struct rzg3s_pcie_host *host,
> > +				   struct resource_entry *entry,
> > +				   int *index);
> >   	const char * const *power_resets;
> >   	const char * const *cfg_resets;
> >   	struct rzg3s_sysc_info sysc_info;
> > @@ -1354,7 +1358,7 @@ static int rzg3s_pcie_parse_map_dma_ranges(struct
> rzg3s_pcie_host *host)
> >   	int i = 0, ret;
> >
> >   	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > -		ret = rzg3s_pcie_set_inbound_windows(host, entry, &i);
> > +		ret = host->data->set_inbound_windows(host, entry, &i);
> >   		if (ret)
> >   			return ret;
> >   	}
> > @@ -1753,6 +1757,7 @@ static const struct rzg3s_pcie_soc_data
> rzg3s_soc_data = {
> >   	.cfg_resets = rzg3s_soc_cfg_resets,
> >   	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
> >   	.init_phy = rzg3s_soc_pcie_init_phy,
> > +	.set_inbound_windows = rzg3s_pcie_set_inbound_windows,
> >   	.sysc_info = {
> >   		.rst_rsm_b = {
> >   			.offset = 0xd74,

RE: [PATCH 06/16] PCI: rzg3s-host: Make SYSC register offsets SoC-specific

[John Madieu]

Hi Claudiu,

Thanks for the review.

> -----Original Message-----
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Sent: Monday, January 19, 2026 7:14 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Subject: Re: [PATCH 06/16] PCI: rzg3s-host: Make SYSC register offsets
> SoC-specific
> 
> Hi, John,
> 
> On 1/14/26 17:33, John Madieu wrote:
> > In preparation for adding RZ/G3E support, move the RST_RSM_B register
> > offset and mask into a SoC-specific data structure. Compared with
> > RZ/G3S, the RZ/G3E SYSC controls different functionalities for the PCIe
> controller.
> >
> > Make SYSC operations conditional on the presence of register offset
> > information, allowing the driver to handle SoCs that don't use the
> > RST_RSM_B signal.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >   drivers/pci/controller/pcie-rzg3s-host.c | 93 +++++++++++++++++-------
> >   1 file changed, 67 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
> > b/drivers/pci/controller/pcie-rzg3s-host.c
> > index 205b60421be1..44728771afa3 100644
> > --- a/drivers/pci/controller/pcie-rzg3s-host.c
> > +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> > @@ -159,10 +159,6 @@
> >
> >   #define RZG3S_PCI_CFG_PCIEC			0x60
> >
> > -/* System controller registers */
> > -#define RZG3S_SYS_PCIE_RST_RSM_B		0xd74
> > -#define RZG3S_SYS_PCIE_RST_RSM_B_MASK		BIT(0)
> > -
> >   /* Maximum number of windows */
> >   #define RZG3S_MAX_WINDOWS			8
> >
> > @@ -174,6 +170,34 @@
> >   /* Timeouts experimentally determined */
> >   #define RZG3S_REQ_ISSUE_TIMEOUT_US		2500
> >
> > +/**
> > + * struct rzg3s_sysc_function - System Controller register function
> > +descriptor
> > + * @offset: Register offset from the System Controller base address
> > + * @mask: Bit mask for the function within the register  */ struct
> > +rzg3s_sysc_function {
> > +	u32 offset;
> > +	u32 mask;
> > +};
> > +
> > +/**
> > + * struct rzg3s_sysc_info - RZ/G3S System Controller function info
> > + * @rst_rsm_b: Reset RSM_B function descriptor  */ struct
> > +rzg3s_sysc_info {
> > +	struct rzg3s_sysc_function rst_rsm_b; };
> > +
> > +/**
> > + * struct rzg3s_sysc - RZ/G3S System Controller descriptor
> > + * @regmap: System controller regmap
> > + * @info: System controller info
> > + */
> > +struct rzg3s_sysc {
> > +	struct regmap *regmap;
> > +	const struct rzg3s_sysc_info *info;
> > +};
> > +
> >   /**
> >    * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
> >    * @domain: IRQ domain
> > @@ -203,6 +227,7 @@ struct rzg3s_pcie_host;
> >    *                power-on
> >    * @cfg_resets: array with the resets that need to be de-asserted
> after
> >    *              configuration
> > + * @sysc_info: SYSC functionalities
> >    * @num_power_resets: number of power resets
> >    * @num_cfg_resets: number of configuration resets
> >    */
> > @@ -210,6 +235,7 @@ struct rzg3s_pcie_soc_data {
> >   	int (*init_phy)(struct rzg3s_pcie_host *host);
> >   	const char * const *power_resets;
> >   	const char * const *cfg_resets;
> > +	struct rzg3s_sysc_info sysc_info;
> >   	u8 num_power_resets;
> >   	u8 num_cfg_resets;
> >   };
> > @@ -233,7 +259,7 @@ struct rzg3s_pcie_port {
> >    * @dev: struct device
> >    * @power_resets: reset control signals that should be set after power
> up
> >    * @cfg_resets: reset control signals that should be set after
> > configuration
> > - * @sysc: SYSC regmap
> > + * @sysc: SYSC descriptor
> >    * @intx_domain: INTx IRQ domain
> >    * @data: SoC specific data
> >    * @msi: MSI data structure
> > @@ -248,7 +274,7 @@ struct rzg3s_pcie_host {
> >   	struct device *dev;
> >   	struct reset_control_bulk_data *power_resets;
> >   	struct reset_control_bulk_data *cfg_resets;
> > -	struct regmap *sysc;
> > +	struct rzg3s_sysc *sysc;
> >   	struct irq_domain *intx_domain;
> >   	const struct rzg3s_pcie_soc_data *data;
> >   	struct rzg3s_pcie_msi msi;
> > @@ -1516,6 +1542,7 @@ static int rzg3s_pcie_probe(struct platform_device
> *pdev)
> >   	struct device_node *sysc_np __free(device_node) =
> >   		of_parse_phandle(np, "renesas,sysc", 0);
> >   	struct rzg3s_pcie_host *host;
> > +	struct rzg3s_sysc *sysc;
> >   	int ret;
> >
> >   	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); @@ -1527,6
> > +1554,13 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
> >   	host->data = device_get_match_data(dev);
> >   	platform_set_drvdata(pdev, host);
> >
> > +	host->sysc = devm_kzalloc(dev, sizeof(*host->sysc), GFP_KERNEL);
> > +	if (!host->sysc)
> > +		return -ENOMEM;
> > +
> > +	sysc = host->sysc;
> > +	sysc->info = &host->data->sysc_info;
> > +
> >   	host->axi = devm_platform_ioremap_resource(pdev, 0);
> >   	if (IS_ERR(host->axi))
> >   		return PTR_ERR(host->axi);
> > @@ -1540,15 +1574,16 @@ static int rzg3s_pcie_probe(struct
> platform_device *pdev)
> >   	if (ret)
> >   		return ret;
> >
> > -	host->sysc = syscon_node_to_regmap(sysc_np);
> > -	if (IS_ERR(host->sysc)) {
> > -		ret = PTR_ERR(host->sysc);
> > +	sysc->regmap = syscon_node_to_regmap(sysc_np);
> > +	if (IS_ERR(sysc->regmap)) {
> > +		ret = PTR_ERR(sysc->regmap);
> >   		goto port_refclk_put;
> >   	}
> >
> > -	ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
> > -				 RZG3S_SYS_PCIE_RST_RSM_B_MASK,
> > -				 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
> > +	ret = regmap_update_bits(sysc->regmap,
> > +				 sysc->info->rst_rsm_b.offset,
> 
> This can stay on the previous line to spare one extra line of code.

Indeed. Noted for V2.

Regards,
John

> 
> The rest LGTM.
> 
> Thank you,
> Claudiu

RE: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[John Madieu]

Hi Claudiu,

Thanks for your review.

> -----Original Message-----
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Sent: Monday, January 19, 2026 3:05 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Subject: Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe
> error path
> 
> Hi, John,
> 
> On 1/14/26 17:33, John Madieu wrote:
> > Fix incorrect reset_control_bulk_deassert() call in the probe error
> > path. When unwinding from a failed pci_host_probe(), the configuration
> > resets should be asserted to restore the hardware to its initial
> > state, not deasserted again.
> >
> > Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host
> > driver")
> 
> The title of the commit with SHA1 7ef502fb35b2 is "PCI: Add Renesas RZ/G3S
> host controller driver".

This patch will be dropped in v2 as we'll go with the single
RZ/G3E implementation.

Regards,
John

> 
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
> > b/drivers/pci/controller/pcie-rzg3s-host.c
> > index 5aa58638903f..c1053f95bc95 100644
> > --- a/drivers/pci/controller/pcie-rzg3s-host.c
> > +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> > @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct
> > platform_device *pdev)
> >
> >   host_probe_teardown:
> >   	rzg3s_pcie_teardown_irqdomain(host);
> > -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> > +	reset_control_bulk_assert(host->data->num_cfg_resets,
> >   				    host->cfg_resets);
> >   rpm_put:
> >   	pm_runtime_put_sync(dev);

RE: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[John Madieu]

Hi Claudiu,

Thanks for your review.

> -----Original Message-----
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> Sent: Monday, January 19, 2026 3:04 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org
> Cc: robh@kernel.org; bhelgaas@google.com; conor+dt@kernel.org; magnus.damm
> <magnus.damm@gmail.com>; Biju Das <biju.das.jz@bp.renesas.com>; linux-
> pci@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> john.madieu@gmail.com
> Subject: Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe
> error path
> 
> Hi, John,
> 
> On 1/14/26 17:33, John Madieu wrote:
> > Fix incorrect reset_control_bulk_deassert() call in the probe error
> > path. When unwinding from a failed pci_host_probe(), the configuration
> > resets should be asserted to restore the hardware to its initial
> > state, not deasserted again.
> >
> > Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host
> > driver")
> 
> The title of the commit with SHA1 7ef502fb35b2 is "PCI: Add Renesas RZ/G3S
> host controller driver". With that addressed:
Thanks for pointing that out. Will fix in v2.

Regards,
John
> 
> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
> > b/drivers/pci/controller/pcie-rzg3s-host.c
> > index 5aa58638903f..c1053f95bc95 100644
> > --- a/drivers/pci/controller/pcie-rzg3s-host.c
> > +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> > @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct
> > platform_device *pdev)
> >
> >   host_probe_teardown:
> >   	rzg3s_pcie_teardown_irqdomain(host);
> > -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> > +	reset_control_bulk_assert(host->data->num_cfg_resets,
> >   				    host->cfg_resets);
> >   rpm_put:
> >   	pm_runtime_put_sync(dev);

RE: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path

[Biju Das]

Hi John,

> -----Original Message-----
> From: John Madieu <john.madieu.xa@bp.renesas.com>
> Sent: 20 January 2026 20:06
> Subject: RE: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in probe error path
> 
> Hi Claudiu,
> 
> Thanks for your review.
> 
> > -----Original Message-----
> > From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> > Sent: Monday, January 19, 2026 3:05 PM
> > To: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> > <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> > kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> > krzk+dt@kernel.org
> > Subject: Re: [PATCH 01/16] PCI: rzg3s-host: Fix reset handling in
> > probe error path
> >
> > Hi, John,
> >
> > On 1/14/26 17:33, John Madieu wrote:
> > > Fix incorrect reset_control_bulk_deassert() call in the probe error
> > > path. When unwinding from a failed pci_host_probe(), the
> > > configuration resets should be asserted to restore the hardware to
> > > its initial state, not deasserted again.
> > >
> > > Fixes: 7ef502fb35b2 ("PCI: rzg3s-host: Add Renesas RZ/G3S SoC host
> > > driver")
> >
> > The title of the commit with SHA1 7ef502fb35b2 is "PCI: Add Renesas
> > RZ/G3S host controller driver".
> 
> This patch will be dropped in v2 as we'll go with the single RZ/G3E implementation.

This is a bug in existing driver, that needs to be fixed, for backporting to stable.

Cheers,
Biju

> 
> Regards,
> John
> 
> >
> > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > ---
> > >   drivers/pci/controller/pcie-rzg3s-host.c | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
> > > b/drivers/pci/controller/pcie-rzg3s-host.c
> > > index 5aa58638903f..c1053f95bc95 100644
> > > --- a/drivers/pci/controller/pcie-rzg3s-host.c
> > > +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> > > @@ -1588,7 +1588,7 @@ static int rzg3s_pcie_probe(struct
> > > platform_device *pdev)
> > >
> > >   host_probe_teardown:
> > >   	rzg3s_pcie_teardown_irqdomain(host);
> > > -	reset_control_bulk_deassert(host->data->num_cfg_resets,
> > > +	reset_control_bulk_assert(host->data->num_cfg_resets,
> > >   				    host->cfg_resets);
> > >   rpm_put:
> > >   	pm_runtime_put_sync(dev);

Re: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

[Geert Uytterhoeven]

On Wed, 14 Jan 2026 at 17:50, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > > >
> > > > The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
> > > > Enable PCIe support.
> > > >
> > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

> > > > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > > @@ -96,6 +96,13 @@ &i2c0 {
> > > >   clock-frequency = <400000>;
> > > >  };
> > > >
> > > > +&pcie {
> > > > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
> > >
> > > This entry to be only in SoC dtsi like RZ/G3S.
> > >
> > > > + pinctrl-0 = <&pcie_pins>;
> > > > + pinctrl-names = "default";
> > >
> > > The pinctrl entries to be moved to board specific file as it will be
> > > used by RZ/G3S, RZ/G3E and Upcoming SoC in future.
> >
> > To summarize, you suggest me to keep only the dma-ranges update in this file and move pinctrl
> > assignment into r9a09g047e57-smarc.dts right ?
>
> Just "status" should be sufficient. Drop dma-ranges and move the pinctrl entries to board dts.

Agreed. After that, the future RZ/G3L DTB build issues related to PCIe are gone.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

[John Madieu]

Hi Geert,

Thanks for your review.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Wednesday, January 21, 2026 11:25 AM
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: John Madieu <john.madieu.xa@bp.renesas.com>; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; geert+renesas@glider.be;
> krzk+dt@kernel.org; robh@kernel.org; bhelgaas@google.com;
> conor+dt@kernel.org; magnus.damm <magnus.damm@gmail.com>; linux-
> pci@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> john.madieu@gmail.com
> Subject: Re: [PATCH 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable
> PCIe
> 
> On Wed, 14 Jan 2026 at 17:50, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > From: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > >
> > > > > The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
> > > > > Enable PCIe support.
> > > > >
> > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> > > > > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > > > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > > > @@ -96,6 +96,13 @@ &i2c0 {
> > > > >   clock-frequency = <400000>;
> > > > >  };
> > > > >
> > > > > +&pcie {
> > > > > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1
> > > > > +0x00000000>;
> > > >
> > > > This entry to be only in SoC dtsi like RZ/G3S.
> > > >
> > > > > + pinctrl-0 = <&pcie_pins>;
> > > > > + pinctrl-names = "default";
> > > >
> > > > The pinctrl entries to be moved to board specific file as it will
> > > > be used by RZ/G3S, RZ/G3E and Upcoming SoC in future.
> > >
> > > To summarize, you suggest me to keep only the dma-ranges update in
> > > this file and move pinctrl assignment into r9a09g047e57-smarc.dts
> right ?
> >
> > Just "status" should be sufficient. Drop dma-ranges and move the pinctrl
> entries to board dts.
> 
> Agreed. After that, the future RZ/G3L DTB build issues related to PCIe are
> gone.
Will be updated in v2.

Regards,
John

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

RE: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[John Madieu]

Hi Geert,

> -----Original Message-----
> From: John Madieu
> Sent: Tuesday, January 20, 2026 8:09 PM
> To: Geert Uytterhoeven <geert@linux-m68k.org>
> Subject: RE: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> init_off clocks
> 
> Hi Geert,
> 
> Thanks for the review.
> 
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: Tuesday, January 20, 2026 11:50 AM
> > To: John Madieu <john.madieu.xa@bp.renesas.com>
> > Subject: Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> > init_off clocks
> >
> > Hi John,
> >
> > On Wed, 14 Jan 2026 at 16:36, John Madieu
> > <john.madieu.xa@bp.renesas.com>
> > wrote:
> > > Some peripherals may be left enabled by the bootloader but should be
> > > explicitly disabled by the kernel to ensure a known initial state.
> > > This is particularly important for PCIe which requires proper
> > > initialization sequencing.
> > >
> > > Add new macros DEF_MOD_INIT_OFF() to declare module clocks that
> > > should be turned off during CPG probe if found in the opposite state.
> > >
> > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > LGTM, so
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > However, I am still wondering if there are any possible bad side
> > effects of disabling the PCIe clocks, e.g. when PCIe is in use
> > (network card, SATA card, ...)?
> 
> I'll test and let you know.

I finally did the test, disabling the PCIe clocks while a WiFi module
connected was performing pings. System got stuck, unusable until next
reboot.

Was that the kind of test you were expecting or did you have a specific
scenario you can share.

Regards,
John

> 
> Regards,
> John
> 
> >
> > Gr{oetje,eeting}s,
> >
> >                         Geert
> >
> > --
> > Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> > geert@linux- m68k.org
> >
> > In personal conversations with technical people, I call myself a hacker.
> > But when I'm talking to journalists I just say "programmer" or
> > something like that.
> >                                 -- Linus Torvalds

Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[Geert Uytterhoeven]

Hi John,

On Thu, 22 Jan 2026 at 17:21, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> > From: John Madieu
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > On Wed, 14 Jan 2026 at 16:36, John Madieu
> > > <john.madieu.xa@bp.renesas.com>
> > > wrote:
> > > > Some peripherals may be left enabled by the bootloader but should be
> > > > explicitly disabled by the kernel to ensure a known initial state.
> > > > This is particularly important for PCIe which requires proper
> > > > initialization sequencing.
> > > >
> > > > Add new macros DEF_MOD_INIT_OFF() to declare module clocks that
> > > > should be turned off during CPG probe if found in the opposite state.
> > > >
> > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > LGTM, so
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > >
> > > However, I am still wondering if there are any possible bad side
> > > effects of disabling the PCIe clocks, e.g. when PCIe is in use
> > > (network card, SATA card, ...)?
> >
> > I'll test and let you know.
>
> I finally did the test, disabling the PCIe clocks while a WiFi module
> connected was performing pings. System got stuck, unusable until next
> reboot.
>
> Was that the kind of test you were expecting or did you have a specific
> scenario you can share.

Not really. I was thinking about a scenario where the bootloader would
configure and use the PCIe device, then transfer control to Linux.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[John Madieu]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Thursday, January 22, 2026 5:29 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> init_off clocks
> 
> Hi John,
> 
> On Thu, 22 Jan 2026 at 17:21, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > > From: John Madieu
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 14 Jan
> > > > 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > wrote:
> > > > > Some peripherals may be left enabled by the bootloader but
> > > > > should be explicitly disabled by the kernel to ensure a known
> initial state.
> > > > > This is particularly important for PCIe which requires proper
> > > > > initialization sequencing.
> > > > >
> > > > > Add new macros DEF_MOD_INIT_OFF() to declare module clocks that
> > > > > should be turned off during CPG probe if found in the opposite
> state.
> > > > >
> > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > LGTM, so
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > >
> > > > However, I am still wondering if there are any possible bad side
> > > > effects of disabling the PCIe clocks, e.g. when PCIe is in use
> > > > (network card, SATA card, ...)?
> > >
> > > I'll test and let you know.
> >
> > I finally did the test, disabling the PCIe clocks while a WiFi module
> > connected was performing pings. System got stuck, unusable until next
> > reboot.
> >
> > Was that the kind of test you were expecting or did you have a
> > specific scenario you can share.
> 
> Not really. I was thinking about a scenario where the bootloader would
> configure and use the PCIe device, then transfer control to Linux.
> 

I can't answer to this exact scenario right now.

The idea of these init_off was from the PCIe host HW manual,
Explicitly requiring tuning the clock off and asserting the reset
as part of its steps, while this is not the case for other IPs.

Regards,
John

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[Lad, Prabhakar]

Hi John,

On Fri, Jan 23, 2026 at 11:29 AM John Madieu
<john.madieu.xa@bp.renesas.com> wrote:
>
> Hi Geert,
>
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: Thursday, January 22, 2026 5:29 PM
> > To: John Madieu <john.madieu.xa@bp.renesas.com>
> > Subject: Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> > init_off clocks
> >
> > Hi John,
> >
> > On Thu, 22 Jan 2026 at 17:21, John Madieu <john.madieu.xa@bp.renesas.com>
> > wrote:
> > > > From: John Madieu
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 14 Jan
> > > > > 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > wrote:
> > > > > > Some peripherals may be left enabled by the bootloader but
> > > > > > should be explicitly disabled by the kernel to ensure a known
> > initial state.
> > > > > > This is particularly important for PCIe which requires proper
> > > > > > initialization sequencing.
> > > > > >
> > > > > > Add new macros DEF_MOD_INIT_OFF() to declare module clocks that
> > > > > > should be turned off during CPG probe if found in the opposite
> > state.
> > > > > >
> > > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > LGTM, so
> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > >
> > > > > However, I am still wondering if there are any possible bad side
> > > > > effects of disabling the PCIe clocks, e.g. when PCIe is in use
> > > > > (network card, SATA card, ...)?
> > > >
> > > > I'll test and let you know.
> > >
> > > I finally did the test, disabling the PCIe clocks while a WiFi module
> > > connected was performing pings. System got stuck, unusable until next
> > > reboot.
> > >
> > > Was that the kind of test you were expecting or did you have a
> > > specific scenario you can share.
> >
> > Not really. I was thinking about a scenario where the bootloader would
> > configure and use the PCIe device, then transfer control to Linux.
> >
>
> I can't answer to this exact scenario right now.
>
> The idea of these init_off was from the PCIe host HW manual,
> Explicitly requiring tuning the clock off and asserting the reset
> as part of its steps, while this is not the case for other IPs.
>
Can the PCIe driver not handle it? ie in the probe explicitly turn off
the clocks + assert reset + continue further (do you see any issue
while doing this from the PCIe driver)?

Cheers,
Prabhakar

RE: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for init_off clocks

[John Madieu]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Friday, January 23, 2026 12:39 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> init_off clocks
> 
> Hi John,
> 
> On Fri, Jan 23, 2026 at 11:29 AM John Madieu
> <john.madieu.xa@bp.renesas.com> wrote:
> >
> > Hi Geert,
> >
> > > -----Original Message-----
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: Thursday, January 22, 2026 5:29 PM
> > > To: John Madieu <john.madieu.xa@bp.renesas.com>
> > > Subject: Re: [PATCH 03/16] clk: renesas: rzv2h-cpg: Add support for
> > > init_off clocks
> > >
> > > Hi John,
> > >
> > > On Thu, 22 Jan 2026 at 17:21, John Madieu
> > > <john.madieu.xa@bp.renesas.com>
> > > wrote:
> > > > > From: John Madieu
> > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 14 Jan
> > > > > > 2026 at 16:36, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > > wrote:
> > > > > > > Some peripherals may be left enabled by the bootloader but
> > > > > > > should be explicitly disabled by the kernel to ensure a
> > > > > > > known
> > > initial state.
> > > > > > > This is particularly important for PCIe which requires
> > > > > > > proper initialization sequencing.
> > > > > > >
> > > > > > > Add new macros DEF_MOD_INIT_OFF() to declare module clocks
> > > > > > > that should be turned off during CPG probe if found in the
> > > > > > > opposite
> > > state.
> > > > > > >
> > > > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > LGTM, so
> > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > >
> > > > > > However, I am still wondering if there are any possible bad
> > > > > > side effects of disabling the PCIe clocks, e.g. when PCIe is
> > > > > > in use (network card, SATA card, ...)?
> > > > >
> > > > > I'll test and let you know.
> > > >
> > > > I finally did the test, disabling the PCIe clocks while a WiFi
> > > > module connected was performing pings. System got stuck, unusable
> > > > until next reboot.
> > > >
> > > > Was that the kind of test you were expecting or did you have a
> > > > specific scenario you can share.
> > >
> > > Not really. I was thinking about a scenario where the bootloader
> > > would configure and use the PCIe device, then transfer control to
> Linux.
> > >
> >
> > I can't answer to this exact scenario right now.
> >
> > The idea of these init_off was from the PCIe host HW manual,
> > Explicitly requiring tuning the clock off and asserting the reset as
> > part of its steps, while this is not the case for other IPs.
> >
> Can the PCIe driver not handle it? ie in the probe explicitly turn off the
> clocks + assert reset + continue further (do you see any issue while doing
> this from the PCIe driver)?

From PCIe driver, it's a bit ugly. For example, clock handling requires
checking current enablement state and act accordingly, which would require
using clock provider API.

Regards,
John

> 
> Cheers,
> Prabhakar