From: Randolph <randolph@andestech.com>
To: <linux-kernel@vger.kernel.org>
Cc: <linux-pci@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<devicetree@vger.kernel.org>, <jingoohan1@gmail.com>,
<mani@kernel.org>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <robh@kernel.org>,
<bhelgaas@google.com>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <alex@ghiti.fr>, <aou@eecs.berkeley.edu>,
<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
<ben717@andestech.com>, <inochiama@gmail.com>,
<thippeswamy.havalige@amd.com>, <namcao@linutronix.de>,
<shradha.t@samsung.com>, <pjw@kernel.org>,
<christian.bruel@foss.st.com>, <quic_wenbyao@quicinc.com>,
<vincent.guittot@linaro.org>, <elder@riscstar.com>,
<s-vadapalli@ti.com>, <randolph.sklin@gmail.com>,
<tim609@andestech.com>, Randolph Lin <randolph@andestech.com>
Subject: [PATCH v10 2/4] riscv: dts: qilai: Add PCIe node into the QiLai SoC
Date: Fri, 16 Jan 2026 19:02:32 +0800 [thread overview]
Message-ID: <20260116110234.1908263-3-randolph@andestech.com> (raw)
In-Reply-To: <20260116110234.1908263-1-randolph@andestech.com>
From: Randolph Lin <randolph@andestech.com>
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
index de3de32f8c39..afa7b75a7e7a 100644
--- a/arch/riscv/boot/dts/andes/qilai.dtsi
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -182,5 +182,111 @@ uart0: serial@30300000 {
reg-io-width = <4>;
no-loopback-test;
};
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>,
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>,
+ <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04000000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xf 0x4>,
+ <0 0 0 2 &plic 0xf 0x4>,
+ <0 0 0 3 &plic 0xf 0x4>,
+ <0 0 0 4 &plic 0xf 0x4>;
+ };
+ };
+
+ bus@a0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>,
+ <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>,
+ <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>;
+
+ pcie@a0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04001000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xe 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xe 0x4>,
+ <0 0 0 2 &plic 0xe 0x4>,
+ <0 0 0 3 &plic 0xe 0x4>,
+ <0 0 0 4 &plic 0xe 0x4>;
+ };
+ };
+
+ bus@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>,
+ <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>,
+ <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>;
+
+ pcie@c0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04002000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xd 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xd 0x4>,
+ <0 0 0 2 &plic 0xd 0x4>,
+ <0 0 0 3 &plic 0xd 0x4>,
+ <0 0 0 4 &plic 0xd 0x4>;
+ };
+ };
+
};
};
--
2.34.1
next prev parent reply other threads:[~2026-01-16 11:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-16 11:02 [PATCH v10 0/4] Add support for Andes Qilai SoC PCIe controller Randolph
2026-01-16 11:02 ` [PATCH v10 1/4] dt-bindings: PCI: Add Andes QiLai PCIe support Randolph
2026-01-16 11:02 ` Randolph [this message]
2026-01-16 11:02 ` [PATCH v10 3/4] PCI: qilai: Add Andes QiLai SoC PCIe host driver support Randolph
2026-02-17 14:10 ` Manivannan Sadhasivam
2026-01-16 11:02 ` [PATCH v10 4/4] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph
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