* [PATCH v10 1/4] dt-bindings: PCI: Add Andes QiLai PCIe support
2026-01-16 11:02 [PATCH v10 0/4] Add support for Andes Qilai SoC PCIe controller Randolph
@ 2026-01-16 11:02 ` Randolph
2026-01-16 11:02 ` [PATCH v10 2/4] riscv: dts: qilai: Add PCIe node into the QiLai SoC Randolph
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Randolph @ 2026-01-16 11:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, christian.bruel, quic_wenbyao, vincent.guittot,
elder, s-vadapalli, randolph.sklin, tim609, Randolph Lin
From: Randolph Lin <randolph@andestech.com>
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Only one example is required in the DTS bindings YAML file.
Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/pci/andestech,qilai-pcie.yaml | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
new file mode 100644
index 000000000000..7eca3be2c8f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes QiLai PCIe host controller
+
+description:
+ Andes QiLai PCIe host controller is based on the Synopsys DesignWare
+ PCI core.
+
+maintainers:
+ - Randolph Lin <randolph@andestech.com>
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: andestech,qilai-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: APB registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: apb
+ - const: config
+
+ ranges:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x0 0x80000000 0x0 0x20000000>,
+ <0x0 0x04000000 0x0 0x00001000>,
+ <0x0 0x00000000 0x0 0x00010000>;
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v10 2/4] riscv: dts: qilai: Add PCIe node into the QiLai SoC
2026-01-16 11:02 [PATCH v10 0/4] Add support for Andes Qilai SoC PCIe controller Randolph
2026-01-16 11:02 ` [PATCH v10 1/4] dt-bindings: PCI: Add Andes QiLai PCIe support Randolph
@ 2026-01-16 11:02 ` Randolph
2026-01-16 11:02 ` [PATCH v10 3/4] PCI: qilai: Add Andes QiLai SoC PCIe host driver support Randolph
2026-01-16 11:02 ` [PATCH v10 4/4] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph
3 siblings, 0 replies; 6+ messages in thread
From: Randolph @ 2026-01-16 11:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, christian.bruel, quic_wenbyao, vincent.guittot,
elder, s-vadapalli, randolph.sklin, tim609, Randolph Lin
From: Randolph Lin <randolph@andestech.com>
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
index de3de32f8c39..afa7b75a7e7a 100644
--- a/arch/riscv/boot/dts/andes/qilai.dtsi
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -182,5 +182,111 @@ uart0: serial@30300000 {
reg-io-width = <4>;
no-loopback-test;
};
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>,
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>,
+ <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04000000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xf 0x4>,
+ <0 0 0 2 &plic 0xf 0x4>,
+ <0 0 0 3 &plic 0xf 0x4>,
+ <0 0 0 4 &plic 0xf 0x4>;
+ };
+ };
+
+ bus@a0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>,
+ <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>,
+ <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>;
+
+ pcie@a0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04001000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xe 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xe 0x4>,
+ <0 0 0 2 &plic 0xe 0x4>,
+ <0 0 0 3 &plic 0xe 0x4>,
+ <0 0 0 4 &plic 0xe 0x4>;
+ };
+ };
+
+ bus@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>,
+ <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>,
+ <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>;
+
+ pcie@c0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04002000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xd 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xd 0x4>,
+ <0 0 0 2 &plic 0xd 0x4>,
+ <0 0 0 3 &plic 0xd 0x4>,
+ <0 0 0 4 &plic 0xd 0x4>;
+ };
+ };
+
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v10 3/4] PCI: qilai: Add Andes QiLai SoC PCIe host driver support
2026-01-16 11:02 [PATCH v10 0/4] Add support for Andes Qilai SoC PCIe controller Randolph
2026-01-16 11:02 ` [PATCH v10 1/4] dt-bindings: PCI: Add Andes QiLai PCIe support Randolph
2026-01-16 11:02 ` [PATCH v10 2/4] riscv: dts: qilai: Add PCIe node into the QiLai SoC Randolph
@ 2026-01-16 11:02 ` Randolph
2026-02-17 14:10 ` Manivannan Sadhasivam
2026-01-16 11:02 ` [PATCH v10 4/4] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph
3 siblings, 1 reply; 6+ messages in thread
From: Randolph @ 2026-01-16 11:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, christian.bruel, quic_wenbyao, vincent.guittot,
elder, s-vadapalli, randolph.sklin, tim609, Randolph Lin
From: Randolph Lin <randolph@andestech.com>
Add driver support for DesignWare based PCIe controller in Andes
QiLai SoC. The driver only supports the Root Complex mode.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
drivers/pci/controller/dwc/Kconfig | 13 ++
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-andes-qilai.c | 198 ++++++++++++++++++
3 files changed, 212 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 519b59422b47..de5ff883e2ba 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -61,6 +61,19 @@ config PCI_MESON
and therefore the driver re-uses the DesignWare core functions to
implement the driver.
+config PCIE_ANDES_QILAI
+ tristate "Andes QiLai PCIe controller"
+ depends on ARCH_ANDES || COMPILE_TEST
+ depends on PCI_MSI
+ select PCIE_DW_HOST
+ help
+ Say Y here to enable PCIe controller support on Andes QiLai SoCs,
+ which operate in Root Complex mode. The Andes QiLai SoC PCIe
+ controller is based on DesignWare IP (5.97a version) and therefore
+ the driver re-uses the DesignWare core functions to implement the
+ driver. The Andes QiLai SoC features three Root Complexes, each
+ operating on PCIe 4.0.
+
config PCIE_ARTPEC6
bool
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 67ba59c02038..9e61458dff00 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
+obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/controller/dwc/pcie-andes-qilai.c b/drivers/pci/controller/dwc/pcie-andes-qilai.c
new file mode 100644
index 000000000000..daa0281abd24
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-andes-qilai.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the PCIe Controller in QiLai from Andes
+ *
+ * Copyright (C) 2025 Andes Technology Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_INTR_CONTROL1 0x15c
+#define PCIE_MSI_CTRL_INT_EN BIT(28)
+
+#define PCIE_LOGIC_COHERENCY_CONTROL3 0x8e8
+
+/*
+ * Refer to Table A4-5 (Memory type encoding) in the
+ * AMBA AXI and ACE Protocol Specification.
+ *
+ * The selected value corresponds to the Memory type field:
+ * "Write-back, Read and Write-allocate".
+ *
+ * The last three rows in the table A4-5 in
+ * AMBA AXI and ACE Protocol Specification:
+ * ARCACHE AWCACHE Memory type
+ * ------------------------------------------------------------------
+ * 1111 (0111) 0111 Write-back Read-allocate
+ * 1011 1111 (1011) Write-back Write-allocate
+ * 1111 1111 Write-back Read and Write-allocate (selected)
+ */
+#define IOCP_ARCACHE 0b1111
+#define IOCP_AWCACHE 0b1111
+
+#define PCIE_CFG_MSTR_ARCACHE_MODE GENMASK(6, 3)
+#define PCIE_CFG_MSTR_AWCACHE_MODE GENMASK(14, 11)
+#define PCIE_CFG_MSTR_ARCACHE_VALUE GENMASK(22, 19)
+#define PCIE_CFG_MSTR_AWCACHE_VALUE GENMASK(30, 27)
+
+#define PCIE_GEN_CONTROL2 0x54
+#define PCIE_CFG_LTSSM_EN BIT(0)
+
+#define PCIE_REGS_PCIE_SII_PM_STATE 0xc0
+#define SMLH_LINK_UP BIT(6)
+#define RDLH_LINK_UP BIT(7)
+#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP)
+
+struct qilai_pcie {
+ struct dw_pcie pci;
+ void __iomem *apb_base;
+};
+
+#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci)
+
+static bool qilai_pcie_link_up(struct dw_pcie *pci)
+{
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+ u32 val;
+
+ /* Read smlh & rdlh link up by checking debug port */
+ val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE);
+
+ return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP;
+}
+
+static int qilai_pcie_start_link(struct dw_pcie *pci)
+{
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+ u32 val;
+
+ val = readl(pcie->apb_base + PCIE_GEN_CONTROL2);
+ val |= PCIE_CFG_LTSSM_EN;
+ writel(val, pcie->apb_base + PCIE_GEN_CONTROL2);
+
+ return 0;
+}
+
+static const struct dw_pcie_ops qilai_pcie_ops = {
+ .link_up = qilai_pcie_link_up,
+ .start_link = qilai_pcie_start_link,
+};
+
+/*
+ * Set up the QiLai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to the
+ * Write-Back, Read and Write Allocate mode.
+ *
+ * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as the
+ * system cache. The IOCP HW helps maintain cache monitoring, ensuring that
+ * the device can snoop data from/to the cache.
+ */
+static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ u32 val;
+
+ dw_pcie_dbi_ro_wr_en(pci);
+
+ dw_pcie_read(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
+ sizeof(val), &val);
+ FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE);
+ dw_pcie_write(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
+ sizeof(val), val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
+}
+
+static void qilai_pcie_enable_msi(struct qilai_pcie *pcie)
+{
+ u32 val;
+
+ val = readl(pcie->apb_base + PCIE_INTR_CONTROL1);
+ val |= PCIE_MSI_CTRL_INT_EN;
+ writel(val, pcie->apb_base + PCIE_INTR_CONTROL1);
+}
+
+static int qilai_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+
+ qilai_pcie_enable_msi(pcie);
+
+ return 0;
+}
+
+static void qilai_pcie_host_post_init(struct dw_pcie_rp *pp)
+{
+ qilai_pcie_iocp_cache_setup(pp);
+}
+
+static const struct dw_pcie_host_ops qilai_pcie_host_ops = {
+ .init = qilai_pcie_host_init,
+ .post_init = qilai_pcie_host_post_init,
+};
+
+static int qilai_pcie_probe(struct platform_device *pdev)
+{
+ struct qilai_pcie *pcie;
+ struct dw_pcie *pci;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pcie);
+
+ pci = &pcie->pci;
+ pcie->pci.dev = dev;
+ pcie->pci.ops = &qilai_pcie_ops;
+ pcie->pci.pp.ops = &qilai_pcie_host_ops;
+ pci->use_parent_dt_ranges = true;
+
+ dw_pcie_cap_set(&pcie->pci, REQ_RES);
+
+ pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
+ if (IS_ERR(pcie->apb_base))
+ return PTR_ERR(pcie->apb_base);
+
+ ret = dw_pcie_host_init(&pcie->pci.pp);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to initialize PCIe host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qilai_pcie_of_match[] = {
+ { .compatible = "andestech,qilai-pcie" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qilai_pcie_of_match);
+
+static struct platform_driver qilai_pcie_driver = {
+ .probe = qilai_pcie_probe,
+ .driver = {
+ .name = "qilai-pcie",
+ .of_match_table = qilai_pcie_of_match,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+};
+
+builtin_platform_driver(qilai_pcie_driver);
+
+MODULE_AUTHOR("Randolph Lin <randolph@andestech.com>");
+MODULE_DESCRIPTION("Andes QiLai PCIe driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v10 3/4] PCI: qilai: Add Andes QiLai SoC PCIe host driver support
2026-01-16 11:02 ` [PATCH v10 3/4] PCI: qilai: Add Andes QiLai SoC PCIe host driver support Randolph
@ 2026-02-17 14:10 ` Manivannan Sadhasivam
0 siblings, 0 replies; 6+ messages in thread
From: Manivannan Sadhasivam @ 2026-02-17 14:10 UTC (permalink / raw)
To: Randolph
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex,
aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, christian.bruel,
quic_wenbyao, vincent.guittot, elder, s-vadapalli, randolph.sklin,
tim609
On Fri, Jan 16, 2026 at 07:02:33PM +0800, Randolph wrote:
> From: Randolph Lin <randolph@andestech.com>
>
> Add driver support for DesignWare based PCIe controller in Andes
> QiLai SoC. The driver only supports the Root Complex mode.
>
> Signed-off-by: Randolph Lin <randolph@andestech.com>
Just a couple of nits. Overall this driver LGTM!
> ---
> drivers/pci/controller/dwc/Kconfig | 13 ++
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-andes-qilai.c | 198 ++++++++++++++++++
> 3 files changed, 212 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index 519b59422b47..de5ff883e2ba 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -61,6 +61,19 @@ config PCI_MESON
> and therefore the driver re-uses the DesignWare core functions to
> implement the driver.
>
> +config PCIE_ANDES_QILAI
> + tristate "Andes QiLai PCIe controller"
> + depends on ARCH_ANDES || COMPILE_TEST
> + depends on PCI_MSI
> + select PCIE_DW_HOST
> + help
> + Say Y here to enable PCIe controller support on Andes QiLai SoCs,
> + which operate in Root Complex mode. The Andes QiLai SoC PCIe
> + controller is based on DesignWare IP (5.97a version) and therefore
Avoid mentioning IP revision here as this driver may evolve to support multiple
IP versions.
> + the driver re-uses the DesignWare core functions to implement the
> + driver. The Andes QiLai SoC features three Root Complexes, each
> + operating on PCIe 4.0.
> +
> config PCIE_ARTPEC6
> bool
>
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index 67ba59c02038..9e61458dff00 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
> obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
> obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
> +obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
> obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
> obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
> obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/controller/dwc/pcie-andes-qilai.c b/drivers/pci/controller/dwc/pcie-andes-qilai.c
> new file mode 100644
> index 000000000000..daa0281abd24
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-andes-qilai.c
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for the PCIe Controller in QiLai from Andes
> + *
> + * Copyright (C) 2025 Andes Technology Corporation
2026
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +
> +#include "pcie-designware.h"
> +
> +#define PCIE_INTR_CONTROL1 0x15c
> +#define PCIE_MSI_CTRL_INT_EN BIT(28)
> +
> +#define PCIE_LOGIC_COHERENCY_CONTROL3 0x8e8
> +
> +/*
> + * Refer to Table A4-5 (Memory type encoding) in the
> + * AMBA AXI and ACE Protocol Specification.
> + *
> + * The selected value corresponds to the Memory type field:
> + * "Write-back, Read and Write-allocate".
> + *
> + * The last three rows in the table A4-5 in
> + * AMBA AXI and ACE Protocol Specification:
> + * ARCACHE AWCACHE Memory type
> + * ------------------------------------------------------------------
> + * 1111 (0111) 0111 Write-back Read-allocate
> + * 1011 1111 (1011) Write-back Write-allocate
> + * 1111 1111 Write-back Read and Write-allocate (selected)
> + */
> +#define IOCP_ARCACHE 0b1111
> +#define IOCP_AWCACHE 0b1111
> +
> +#define PCIE_CFG_MSTR_ARCACHE_MODE GENMASK(6, 3)
> +#define PCIE_CFG_MSTR_AWCACHE_MODE GENMASK(14, 11)
> +#define PCIE_CFG_MSTR_ARCACHE_VALUE GENMASK(22, 19)
> +#define PCIE_CFG_MSTR_AWCACHE_VALUE GENMASK(30, 27)
> +
> +#define PCIE_GEN_CONTROL2 0x54
> +#define PCIE_CFG_LTSSM_EN BIT(0)
> +
> +#define PCIE_REGS_PCIE_SII_PM_STATE 0xc0
> +#define SMLH_LINK_UP BIT(6)
> +#define RDLH_LINK_UP BIT(7)
> +#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP)
> +
> +struct qilai_pcie {
> + struct dw_pcie pci;
> + void __iomem *apb_base;
> +};
> +
> +#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci)
> +
> +static bool qilai_pcie_link_up(struct dw_pcie *pci)
> +{
> + struct qilai_pcie *pcie = to_qilai_pcie(pci);
> + u32 val;
> +
> + /* Read smlh & rdlh link up by checking debug port */
No need of this comment.
> + val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE);
> +
> + return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP;
Use FIELD_ macros throughout the driver.
> +}
> +
> +static int qilai_pcie_start_link(struct dw_pcie *pci)
> +{
> + struct qilai_pcie *pcie = to_qilai_pcie(pci);
> + u32 val;
> +
> + val = readl(pcie->apb_base + PCIE_GEN_CONTROL2);
> + val |= PCIE_CFG_LTSSM_EN;
> + writel(val, pcie->apb_base + PCIE_GEN_CONTROL2);
> +
> + return 0;
> +}
> +
> +static const struct dw_pcie_ops qilai_pcie_ops = {
> + .link_up = qilai_pcie_link_up,
> + .start_link = qilai_pcie_start_link,
> +};
> +
> +/*
> + * Set up the QiLai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to the
> + * Write-Back, Read and Write Allocate mode.
> + *
> + * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as the
> + * system cache. The IOCP HW helps maintain cache monitoring, ensuring that
> + * the device can snoop data from/to the cache.
If the IP allows device to snoop data to/from the cache, the controller should
be marked as 'dma-coherent' in devicetree. And you need to add this property in
the binding too.
> + */
> +static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + u32 val;
> +
> + dw_pcie_dbi_ro_wr_en(pci);
> +
> + dw_pcie_read(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
> + sizeof(val), &val);
> + FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE);
> + FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE);
> + FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE);
> + FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE);
> + dw_pcie_write(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
> + sizeof(val), val);
> +
> + dw_pcie_dbi_ro_wr_dis(pci);
> +}
> +
> +static void qilai_pcie_enable_msi(struct qilai_pcie *pcie)
> +{
> + u32 val;
> +
> + val = readl(pcie->apb_base + PCIE_INTR_CONTROL1);
> + val |= PCIE_MSI_CTRL_INT_EN;
> + writel(val, pcie->apb_base + PCIE_INTR_CONTROL1);
> +}
> +
> +static int qilai_pcie_host_init(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct qilai_pcie *pcie = to_qilai_pcie(pci);
> +
> + qilai_pcie_enable_msi(pcie);
> +
> + return 0;
> +}
> +
> +static void qilai_pcie_host_post_init(struct dw_pcie_rp *pp)
> +{
> + qilai_pcie_iocp_cache_setup(pp);
> +}
> +
> +static const struct dw_pcie_host_ops qilai_pcie_host_ops = {
> + .init = qilai_pcie_host_init,
> + .post_init = qilai_pcie_host_post_init,
> +};
> +
> +static int qilai_pcie_probe(struct platform_device *pdev)
> +{
> + struct qilai_pcie *pcie;
> + struct dw_pcie *pci;
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
> + if (!pcie)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, pcie);
> +
> + pci = &pcie->pci;
> + pcie->pci.dev = dev;
> + pcie->pci.ops = &qilai_pcie_ops;
> + pcie->pci.pp.ops = &qilai_pcie_host_ops;
> + pci->use_parent_dt_ranges = true;
> +
> + dw_pcie_cap_set(&pcie->pci, REQ_RES);
> +
> + pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
> + if (IS_ERR(pcie->apb_base))
> + return PTR_ERR(pcie->apb_base);
> +
Mark controller PM runtime status as enabled:
pm_runtime_set_active(dev);
pm_runtime_no_callbacks(dev);
devm_pm_runtime_enable(dev);
> + ret = dw_pcie_host_init(&pcie->pci.pp);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to initialize PCIe host\n");
return dev_err_probe()...
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v10 4/4] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver
2026-01-16 11:02 [PATCH v10 0/4] Add support for Andes Qilai SoC PCIe controller Randolph
` (2 preceding siblings ...)
2026-01-16 11:02 ` [PATCH v10 3/4] PCI: qilai: Add Andes QiLai SoC PCIe host driver support Randolph
@ 2026-01-16 11:02 ` Randolph
3 siblings, 0 replies; 6+ messages in thread
From: Randolph @ 2026-01-16 11:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, christian.bruel, quic_wenbyao, vincent.guittot,
elder, s-vadapalli, randolph.sklin, tim609, Randolph Lin
From: Randolph Lin <randolph@andestech.com>
Here add maintainer information for Andes QiLai PCIe driver.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0d044a58cbfe..a441db539d57 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19898,6 +19898,13 @@ S: Supported
F: Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
F: drivers/pci/controller/pcie-altera.c
+PCI DRIVER FOR ANDES QILAI PCIE
+M: Randolph Lin <randolph@andestech.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
+F: drivers/pci/controller/dwc/pcie-andes-qilai.c
+
PCI DRIVER FOR APPLIEDMICRO XGENE
M: Toan Le <toan@os.amperecomputing.com>
L: linux-pci@vger.kernel.org
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread