[PATCH v3 0/3] mailbox: qcom-ipcc: Add dt-bindings and header files for Kaanapali and Glymur Platforms

[PATCH v3 0/3] mailbox: qcom-ipcc: Add dt-bindings and header files for Kaanapali and Glymur Platforms

[Jingyi Wang]

Add dt-bindings and header files for the Inter-Processor Communication
Controller on Kaanapali and Glymur platforms.

On earlier platforms, Inter Process Communication Controller (IPCC) used
virtual client IDs and performed virtual-to-physical mapping in hardware,
so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
platforms. Physical client IDs instead of virtual client IDs are used for
qcom new platforms like Kaanapali and Glymur, which will be parsed by the
devicetree and passed to hardware to use Physical client IDs directly,
so header files are defined under dts.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
Changes in v3:
- Move header files from dt-binding to dts - Krzysztof
- Reorganize patches
- more detailed information in commit msg - Bjorn
- Link to v2: https://lore.kernel.org/r/20251029-knp-ipcc-v2-0-8ba303ab82de@oss.qualcomm.com

Changes in v2:
- Add separate header files for different platforms
- Merge binding and header file in one patch
- squash glymur ipcc change from: https://lore.kernel.org/linux-arm-msm/20250924183726.509202-1-sibi.sankar@oss.qualcomm.com/T/#m186ef6ceb50936185d07b81e2d36228a5a361d34
- Link to v1: https://lore.kernel.org/r/20250924-knp-ipcc-v1-1-5d9e9cb59ad4@oss.qualcomm.com

---
Jingyi Wang (2):
      dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms
      arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform

Sibi Sankar (1):
      arm64: dts: qcom: Add header file for IPCC physical client IDs on Glymur platform

 .../devicetree/bindings/mailbox/qcom-ipcc.yaml     |  2 +
 arch/arm64/boot/dts/qcom/glymur-ipcc.h             | 68 ++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/kaanapali-ipcc.h          | 58 ++++++++++++++++++
 3 files changed, 128 insertions(+)
---
base-commit: aaa9c3550b60d6259d6ea8b1175ade8d1242444e
change-id: 20251028-knp-ipcc-6b4189f71121

Best regards,
-- 
Jingyi Wang <jingyi.wang@oss.qualcomm.com>

[PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Jingyi Wang]

Document the Inter-Processor Communication Controller on the Qualcomm
Kaanapali and Glymur Platforms, which will be used to route interrupts
across various subsystems found on the SoC.

Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index e5c423130db6..7c4d6170491d 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,6 +24,8 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,glymur-ipcc
+          - qcom,kaanapali-ipcc
           - qcom,milos-ipcc
           - qcom,qcs8300-ipcc
           - qcom,qdu1000-ipcc

-- 
2.25.1

[PATCH v3 2/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform

[Jingyi Wang]

On earlier platforms, Inter Process Communication Controller (IPCC) used
virtual client IDs and performed virtual-to-physical mapping in hardware,
so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
platforms. Physical client IDs instead of virtual client IDs are used for
qcom new platforms like Kaanapali, which will be parsed by the devicetree
and passed to hardware to use Physical client IDs directly. Since physical
client IDs could vary across platforms, add a corresponding header file
for the Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali-ipcc.h | 58 +++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
new file mode 100644
index 000000000000..125375a4aac0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H
+#define __DTS_KAANAPALI_MAILBOX_IPCC_H
+
+/* Physical client IDs */
+#define IPCC_MPROC_AOP			0
+#define IPCC_MPROC_TZ			1
+#define IPCC_MPROC_MPSS			2
+#define IPCC_MPROC_LPASS		3
+#define IPCC_MPROC_SDC			4
+#define IPCC_MPROC_CDSP			5
+#define IPCC_MPROC_APSS			6
+#define IPCC_MPROC_SOCCP		13
+#define IPCC_MPROC_DCP			14
+#define IPCC_MPROC_SPSS			15
+#define IPCC_MPROC_TME			16
+#define IPCC_MPROC_WPSS			17
+
+#define IPCC_COMPUTE_L0_CDSP		2
+#define IPCC_COMPUTE_L0_APSS		3
+#define IPCC_COMPUTE_L0_GPU		4
+#define IPCC_COMPUTE_L0_CVP		8
+#define IPCC_COMPUTE_L0_CAM		9
+#define IPCC_COMPUTE_L0_CAM1		10
+#define IPCC_COMPUTE_L0_DCP		11
+#define IPCC_COMPUTE_L0_VPU		12
+#define IPCC_COMPUTE_L0_SOCCP		16
+
+#define IPCC_COMPUTE_L1_CDSP		2
+#define IPCC_COMPUTE_L1_APSS		3
+#define IPCC_COMPUTE_L1_GPU		4
+#define IPCC_COMPUTE_L1_CVP		8
+#define IPCC_COMPUTE_L1_CAM		9
+#define IPCC_COMPUTE_L1_CAM1		10
+#define IPCC_COMPUTE_L1_DCP		11
+#define IPCC_COMPUTE_L1_VPU		12
+#define IPCC_COMPUTE_L1_SOCCP		16
+
+#define IPCC_PERIPH_CDSP		2
+#define IPCC_PERIPH_APSS		3
+#define IPCC_PERIPH_PCIE0		4
+#define IPCC_PERIPH_PCIE1		5
+
+#define IPCC_FENCE_CDSP			2
+#define IPCC_FENCE_APSS			3
+#define IPCC_FENCE_GPU			4
+#define IPCC_FENCE_CVP			8
+#define IPCC_FENCE_CAM			8
+#define IPCC_FENCE_CAM1			10
+#define IPCC_FENCE_DCP			11
+#define IPCC_FENCE_VPU			20
+#define IPCC_FENCE_SOCCP		24
+
+#endif

-- 
2.25.1

[PATCH v3 3/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Glymur platform

[Jingyi Wang]

From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>

Physical client IDs are used on Glymur Inter Process Communication
Controller (IPCC), add a corresponding header file.

Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur-ipcc.h | 68 ++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur-ipcc.h b/arch/arm64/boot/dts/qcom/glymur-ipcc.h
new file mode 100644
index 000000000000..700cd7114909
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/glymur-ipcc.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H
+#define __DTS_GLYMUR_MAILBOX_IPCC_H
+
+/* Glymur physical client IDs */
+#define IPCC_MPROC_AOP			0
+#define IPCC_MPROC_TZ			1
+#define IPCC_MPROC_MPSS			2
+#define IPCC_MPROC_LPASS		3
+#define IPCC_MPROC_SLPI			4
+#define IPCC_MPROC_SDC			5
+#define IPCC_MPROC_CDSP			6
+#define IPCC_MPROC_NPU			7
+#define IPCC_MPROC_APSS			8
+#define IPCC_MPROC_GPU			9
+#define IPCC_MPROC_ICP			11
+#define IPCC_MPROC_VPU			12
+#define IPCC_MPROC_PCIE0		13
+#define IPCC_MPROC_PCIE1		14
+#define IPCC_MPROC_PCIE2		15
+#define IPCC_MPROC_SPSS			16
+#define IPCC_MPROC_PCIE3		19
+#define IPCC_MPROC_PCIE4		20
+#define IPCC_MPROC_PCIE5		21
+#define IPCC_MPROC_PCIE6		22
+#define IPCC_MPROC_TME			23
+#define IPCC_MPROC_WPSS			24
+#define IPCC_MPROC_PCIE7		44
+#define IPCC_MPROC_SOCCP		46
+
+#define IPCC_COMPUTE_L0_LPASS		0
+#define IPCC_COMPUTE_L0_CDSP		1
+#define IPCC_COMPUTE_L0_APSS		2
+#define IPCC_COMPUTE_L0_GPU		3
+#define IPCC_COMPUTE_L0_CVP		6
+#define IPCC_COMPUTE_L0_ICP		7
+#define IPCC_COMPUTE_L0_VPU		8
+#define IPCC_COMPUTE_L0_DPU		9
+#define IPCC_COMPUTE_L0_SOCCP		11
+
+#define IPCC_COMPUTE_L1_LPASS		0
+#define IPCC_COMPUTE_L1_CDSP		1
+#define IPCC_COMPUTE_L1_APSS		2
+#define IPCC_COMPUTE_L1_GPU		3
+#define IPCC_COMPUTE_L1_CVP		6
+#define IPCC_COMPUTE_L1_ICP		7
+#define IPCC_COMPUTE_L1_VPU		8
+#define IPCC_COMPUTE_L1_DPU		9
+#define IPCC_COMPUTE_L1_SOCCP		11
+
+#define IPCC_PERIPH_LPASS		0
+#define IPCC_PERIPH_APSS		1
+#define IPCC_PERIPH_PCIE0		2
+#define IPCC_PERIPH_PCIE1		3
+#define IPCC_PERIPH_PCIE2		6
+#define IPCC_PERIPH_PCIE3		7
+#define IPCC_PERIPH_PCIE4		8
+#define IPCC_PERIPH_PCIE5		9
+#define IPCC_PERIPH_PCIE6		10
+#define IPCC_PERIPH_PCIE7		11
+#define IPCC_PERIPH_SOCCP		13
+#define IPCC_PERIPH_WPSS		16
+
+#endif

-- 
2.25.1

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Krzysztof Kozlowski]

On 31/10/2025 08:41, Jingyi Wang wrote:
> Document the Inter-Processor Communication Controller on the Qualcomm
> Kaanapali and Glymur Platforms, which will be used to route interrupts
> across various subsystems found on the SoC.
> 
> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 3/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Glymur platform

[Krzysztof Kozlowski]

On 31/10/2025 08:41, Jingyi Wang wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> 
> Physical client IDs are used on Glymur Inter Process Communication
> Controller (IPCC), add a corresponding header file.
> 
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur-ipcc.h | 68 ++++++++++++++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
> 



Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 2/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform

[Krzysztof Kozlowski]

On 31/10/2025 08:41, Jingyi Wang wrote:
> On earlier platforms, Inter Process Communication Controller (IPCC) used
> virtual client IDs and performed virtual-to-physical mapping in hardware,
> so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
> platforms. Physical client IDs instead of virtual client IDs are used for
> qcom new platforms like Kaanapali, which will be parsed by the devicetree
> and passed to hardware to use Physical client IDs directly. Since physical
> client IDs could vary across platforms, add a corresponding header file
> for the Kaanapali platform.
> 
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Bjorn Andersson]

On Fri, Oct 31, 2025 at 12:41:44AM -0700, Jingyi Wang wrote:
> Document the Inter-Processor Communication Controller on the Qualcomm
> Kaanapali and Glymur Platforms, which will be used to route interrupts
> across various subsystems found on the SoC.
> 
> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>

Reviewed-by: Bjorn Andersson <andersson@kernel.org>

Regards,
Bjorn

> ---
>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> index e5c423130db6..7c4d6170491d 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> @@ -24,6 +24,8 @@ properties:
>    compatible:
>      items:
>        - enum:
> +          - qcom,glymur-ipcc
> +          - qcom,kaanapali-ipcc
>            - qcom,milos-ipcc
>            - qcom,qcs8300-ipcc
>            - qcom,qdu1000-ipcc
> 
> -- 
> 2.25.1
> 
> 

Re: [PATCH v3 2/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform

[Bjorn Andersson]

On Fri, Oct 31, 2025 at 12:41:45AM -0700, Jingyi Wang wrote:

Whenever you have a subject line that ends in "on <soc/platform>",
that's a good indicator that you're missing something in the subject
prefix.

Compare:
arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform

with:
arm64: dts: qcom: kaanapali: Add IPCC client IDs


Also, now that this is "devicetree", it would make sense to merge them
together with the users. Or at least after we've introduced
kaanapali.dtsi...


I don't think you need to resubmit this though, I can fix up the subject
when I merge. But please get to the point where it makes sense to merge
them as fast as possible.

Regards,
Bjorn

> On earlier platforms, Inter Process Communication Controller (IPCC) used
> virtual client IDs and performed virtual-to-physical mapping in hardware,
> so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
> platforms. Physical client IDs instead of virtual client IDs are used for
> qcom new platforms like Kaanapali, which will be parsed by the devicetree
> and passed to hardware to use Physical client IDs directly. Since physical
> client IDs could vary across platforms, add a corresponding header file
> for the Kaanapali platform.
> 
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali-ipcc.h | 58 +++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
> new file mode 100644
> index 000000000000..125375a4aac0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
> @@ -0,0 +1,58 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H
> +#define __DTS_KAANAPALI_MAILBOX_IPCC_H
> +
> +/* Physical client IDs */
> +#define IPCC_MPROC_AOP			0
> +#define IPCC_MPROC_TZ			1
> +#define IPCC_MPROC_MPSS			2
> +#define IPCC_MPROC_LPASS		3
> +#define IPCC_MPROC_SDC			4
> +#define IPCC_MPROC_CDSP			5
> +#define IPCC_MPROC_APSS			6
> +#define IPCC_MPROC_SOCCP		13
> +#define IPCC_MPROC_DCP			14
> +#define IPCC_MPROC_SPSS			15
> +#define IPCC_MPROC_TME			16
> +#define IPCC_MPROC_WPSS			17
> +
> +#define IPCC_COMPUTE_L0_CDSP		2
> +#define IPCC_COMPUTE_L0_APSS		3
> +#define IPCC_COMPUTE_L0_GPU		4
> +#define IPCC_COMPUTE_L0_CVP		8
> +#define IPCC_COMPUTE_L0_CAM		9
> +#define IPCC_COMPUTE_L0_CAM1		10
> +#define IPCC_COMPUTE_L0_DCP		11
> +#define IPCC_COMPUTE_L0_VPU		12
> +#define IPCC_COMPUTE_L0_SOCCP		16
> +
> +#define IPCC_COMPUTE_L1_CDSP		2
> +#define IPCC_COMPUTE_L1_APSS		3
> +#define IPCC_COMPUTE_L1_GPU		4
> +#define IPCC_COMPUTE_L1_CVP		8
> +#define IPCC_COMPUTE_L1_CAM		9
> +#define IPCC_COMPUTE_L1_CAM1		10
> +#define IPCC_COMPUTE_L1_DCP		11
> +#define IPCC_COMPUTE_L1_VPU		12
> +#define IPCC_COMPUTE_L1_SOCCP		16
> +
> +#define IPCC_PERIPH_CDSP		2
> +#define IPCC_PERIPH_APSS		3
> +#define IPCC_PERIPH_PCIE0		4
> +#define IPCC_PERIPH_PCIE1		5
> +
> +#define IPCC_FENCE_CDSP			2
> +#define IPCC_FENCE_APSS			3
> +#define IPCC_FENCE_GPU			4
> +#define IPCC_FENCE_CVP			8
> +#define IPCC_FENCE_CAM			8
> +#define IPCC_FENCE_CAM1			10
> +#define IPCC_FENCE_DCP			11
> +#define IPCC_FENCE_VPU			20
> +#define IPCC_FENCE_SOCCP		24
> +
> +#endif
> 
> -- 
> 2.25.1
> 

Re: [PATCH v3 2/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform

[Jingyi Wang]

On 11/2/2025 3:07 AM, Bjorn Andersson wrote:
> On Fri, Oct 31, 2025 at 12:41:45AM -0700, Jingyi Wang wrote:
> 
> Whenever you have a subject line that ends in "on <soc/platform>",
> that's a good indicator that you're missing something in the subject
> prefix.
> 
> Compare:
> arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform
> 
> with:
> arm64: dts: qcom: kaanapali: Add IPCC client IDs
> 
> 
> Also, now that this is "devicetree", it would make sense to merge them
> together with the users. Or at least after we've introduced
> kaanapali.dtsi...
> 
> 
> I don't think you need to resubmit this though, I can fix up the subject
> when I merge. But please get to the point where it makes sense to merge
> them as fast as possible.
> 
> Regards,
> Bjorn
> 

Got it.

Thanks,
Jingyi

>> On earlier platforms, Inter Process Communication Controller (IPCC) used
>> virtual client IDs and performed virtual-to-physical mapping in hardware,
>> so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
>> platforms. Physical client IDs instead of virtual client IDs are used for
>> qcom new platforms like Kaanapali, which will be parsed by the devicetree
>> and passed to hardware to use Physical client IDs directly. Since physical
>> client IDs could vary across platforms, add a corresponding header file
>> for the Kaanapali platform.
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/kaanapali-ipcc.h | 58 +++++++++++++++++++++++++++++++
>>  1 file changed, 58 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
>> new file mode 100644
>> index 000000000000..125375a4aac0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
>> @@ -0,0 +1,58 @@
>> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H
>> +#define __DTS_KAANAPALI_MAILBOX_IPCC_H
>> +
>> +/* Physical client IDs */
>> +#define IPCC_MPROC_AOP			0
>> +#define IPCC_MPROC_TZ			1
>> +#define IPCC_MPROC_MPSS			2
>> +#define IPCC_MPROC_LPASS		3
>> +#define IPCC_MPROC_SDC			4
>> +#define IPCC_MPROC_CDSP			5
>> +#define IPCC_MPROC_APSS			6
>> +#define IPCC_MPROC_SOCCP		13
>> +#define IPCC_MPROC_DCP			14
>> +#define IPCC_MPROC_SPSS			15
>> +#define IPCC_MPROC_TME			16
>> +#define IPCC_MPROC_WPSS			17
>> +
>> +#define IPCC_COMPUTE_L0_CDSP		2
>> +#define IPCC_COMPUTE_L0_APSS		3
>> +#define IPCC_COMPUTE_L0_GPU		4
>> +#define IPCC_COMPUTE_L0_CVP		8
>> +#define IPCC_COMPUTE_L0_CAM		9
>> +#define IPCC_COMPUTE_L0_CAM1		10
>> +#define IPCC_COMPUTE_L0_DCP		11
>> +#define IPCC_COMPUTE_L0_VPU		12
>> +#define IPCC_COMPUTE_L0_SOCCP		16
>> +
>> +#define IPCC_COMPUTE_L1_CDSP		2
>> +#define IPCC_COMPUTE_L1_APSS		3
>> +#define IPCC_COMPUTE_L1_GPU		4
>> +#define IPCC_COMPUTE_L1_CVP		8
>> +#define IPCC_COMPUTE_L1_CAM		9
>> +#define IPCC_COMPUTE_L1_CAM1		10
>> +#define IPCC_COMPUTE_L1_DCP		11
>> +#define IPCC_COMPUTE_L1_VPU		12
>> +#define IPCC_COMPUTE_L1_SOCCP		16
>> +
>> +#define IPCC_PERIPH_CDSP		2
>> +#define IPCC_PERIPH_APSS		3
>> +#define IPCC_PERIPH_PCIE0		4
>> +#define IPCC_PERIPH_PCIE1		5
>> +
>> +#define IPCC_FENCE_CDSP			2
>> +#define IPCC_FENCE_APSS			3
>> +#define IPCC_FENCE_GPU			4
>> +#define IPCC_FENCE_CVP			8
>> +#define IPCC_FENCE_CAM			8
>> +#define IPCC_FENCE_CAM1			10
>> +#define IPCC_FENCE_DCP			11
>> +#define IPCC_FENCE_VPU			20
>> +#define IPCC_FENCE_SOCCP		24
>> +
>> +#endif
>>
>> -- 
>> 2.25.1
>>

Re: (subset) [PATCH v3 0/3] mailbox: qcom-ipcc: Add dt-bindings and header files for Kaanapali and Glymur Platforms

[Bjorn Andersson]

On Fri, 31 Oct 2025 00:41:43 -0700, Jingyi Wang wrote:
> Add dt-bindings and header files for the Inter-Processor Communication
> Controller on Kaanapali and Glymur platforms.
> 
> On earlier platforms, Inter Process Communication Controller (IPCC) used
> virtual client IDs and performed virtual-to-physical mapping in hardware,
> so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
> platforms. Physical client IDs instead of virtual client IDs are used for
> qcom new platforms like Kaanapali and Glymur, which will be parsed by the
> devicetree and passed to hardware to use Physical client IDs directly,
> so header files are defined under dts.
> 
> [...]

Applied, thanks!

[2/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Kaanapali platform
      commit: f4a269eb1328d855314c858b5e903eca92ca3b36
[3/3] arm64: dts: qcom: Add header file for IPCC physical client IDs on Glymur platform
      commit: e36c38c91f5f3c07e65c58a0143e3124754a9030

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Rob Herring]

On Fri, Oct 31, 2025 at 12:41:44AM -0700, Jingyi Wang wrote:
> Document the Inter-Processor Communication Controller on the Qualcomm
> Kaanapali and Glymur Platforms, which will be used to route interrupts
> across various subsystems found on the SoC.
> 
> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
>  1 file changed, 2 insertions(+)

I guess no one is going to apply this, so I did.

If your patches don't get applied, please chase the maintainers (Jassi) 
to apply them.

Rob

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Krzysztof Kozlowski]

On 16/01/2026 17:20, Rob Herring wrote:
> On Fri, Oct 31, 2025 at 12:41:44AM -0700, Jingyi Wang wrote:
>> Document the Inter-Processor Communication Controller on the Qualcomm
>> Kaanapali and Glymur Platforms, which will be used to route interrupts
>> across various subsystems found on the SoC.
>>
>> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
>>  1 file changed, 2 insertions(+)
> 
> I guess no one is going to apply this, so I did.
> 
> If your patches don't get applied, please chase the maintainers (Jassi) 
> to apply them.


This or it is an effect of known problem with mailbox and interconnect
subsystems - maintainers never send notifications of applied patches
(neither publicly nor privately like Greg does), so you will never know
if anything gets applied.

This as well could be in the next silently (wasn't in 15th Jan, though).

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Rob Herring]

On Fri, Jan 16, 2026 at 10:25 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 16/01/2026 17:20, Rob Herring wrote:
> > On Fri, Oct 31, 2025 at 12:41:44AM -0700, Jingyi Wang wrote:
> >> Document the Inter-Processor Communication Controller on the Qualcomm
> >> Kaanapali and Glymur Platforms, which will be used to route interrupts
> >> across various subsystems found on the SoC.
> >>
> >> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >> ---
> >>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
> >>  1 file changed, 2 insertions(+)
> >
> > I guess no one is going to apply this, so I did.
> >
> > If your patches don't get applied, please chase the maintainers (Jassi)
> > to apply them.
>
>
> This or it is an effect of known problem with mailbox and interconnect
> subsystems - maintainers never send notifications of applied patches
> (neither publicly nor privately like Greg does), so you will never know
> if anything gets applied.
>
> This as well could be in the next silently (wasn't in 15th Jan, though).

Further investigation finds Jassi did apply this and 3 other patches.
Stephen reported a conflict on 1/6 with another Qcom patch
(conflicting with Bjorn's tree). No reply to Stephen, but *all* the
mbox binding patches were dropped.

Here's what was dropped:

f8f632c18c32 dt-bindings: mbox: add pic64gx mailbox compatibility to
mpfs mailbox
945dc11a38a0 dt-bindings: mailbox: qcom: Add CPUCP mailbox controller
bindings for Kaanapali
66b6e5daa915 dt-bindings: mailbox: qcom: Add IPCC support for
Kaanapali and Glymur Platforms
9a92e22740e6 dt-bindings: mailbox: mediatek,mt8196-vcp-mbox: add mtk
vcp-mbox document

Rob

Re: (subset) [PATCH v3 0/3] mailbox: qcom-ipcc: Add dt-bindings and header files for Kaanapali and Glymur Platforms

[Bjorn Andersson]

On Fri, 31 Oct 2025 00:41:43 -0700, Jingyi Wang wrote:
> Add dt-bindings and header files for the Inter-Processor Communication
> Controller on Kaanapali and Glymur platforms.
> 
> On earlier platforms, Inter Process Communication Controller (IPCC) used
> virtual client IDs and performed virtual-to-physical mapping in hardware,
> so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
> platforms. Physical client IDs instead of virtual client IDs are used for
> qcom new platforms like Kaanapali and Glymur, which will be parsed by the
> devicetree and passed to hardware to use Physical client IDs directly,
> so header files are defined under dts.
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms
      commit: fc12767c19d49663b13ba2def6e4674df041c8a2

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Jassi Brar]

On Fri, Jan 16, 2026 at 11:13 AM Rob Herring <robh@kernel.org> wrote:
>
> On Fri, Jan 16, 2026 at 10:25 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On 16/01/2026 17:20, Rob Herring wrote:
> > > On Fri, Oct 31, 2025 at 12:41:44AM -0700, Jingyi Wang wrote:
> > >> Document the Inter-Processor Communication Controller on the Qualcomm
> > >> Kaanapali and Glymur Platforms, which will be used to route interrupts
> > >> across various subsystems found on the SoC.
> > >>
> > >> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > >> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > >> ---
> > >>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
> > >>  1 file changed, 2 insertions(+)
> > >
> > > I guess no one is going to apply this, so I did.
> > >
> > > If your patches don't get applied, please chase the maintainers (Jassi)
> > > to apply them.
> >
> >
> > This or it is an effect of known problem with mailbox and interconnect
> > subsystems - maintainers never send notifications of applied patches
> > (neither publicly nor privately like Greg does), so you will never know
> > if anything gets applied.
> >
> > This as well could be in the next silently (wasn't in 15th Jan, though).
>
> Further investigation finds Jassi did apply this and 3 other patches.
> Stephen reported a conflict on 1/6 with another Qcom patch
> (conflicting with Bjorn's tree). No reply to Stephen, but *all* the
> mbox binding patches were dropped.
>
> Here's what was dropped:
>
> f8f632c18c32 dt-bindings: mbox: add pic64gx mailbox compatibility to
> mpfs mailbox
> 945dc11a38a0 dt-bindings: mailbox: qcom: Add CPUCP mailbox controller
> bindings for Kaanapali
> 66b6e5daa915 dt-bindings: mailbox: qcom: Add IPCC support for
> Kaanapali and Glymur Platforms
> 9a92e22740e6 dt-bindings: mailbox: mediatek,mt8196-vcp-mbox: add mtk
> vcp-mbox document
>
Yes, I had to reconstruct the mailbox for-next branch because some
patch had an issue and the pr was not merged after a very late fix.
Sorry I didn't realize people not receiving pick-confirmations was so
problematic. I will make sure I reply to every patch that I pick.
Thanks.

Re: [PATCH v3 1/3] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms

[Rob Herring]

On Sun, Jan 18, 2026 at 12:37 PM Jassi Brar <jassisinghbrar@gmail.com> wrote:
>
> On Fri, Jan 16, 2026 at 11:13 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Fri, Jan 16, 2026 at 10:25 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >
> > > On 16/01/2026 17:20, Rob Herring wrote:
> > > > On Fri, Oct 31, 2025 at 12:41:44AM -0700, Jingyi Wang wrote:
> > > >> Document the Inter-Processor Communication Controller on the Qualcomm
> > > >> Kaanapali and Glymur Platforms, which will be used to route interrupts
> > > >> across various subsystems found on the SoC.
> > > >>
> > > >> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > > >> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > > >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > > >> ---
> > > >>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++
> > > >>  1 file changed, 2 insertions(+)
> > > >
> > > > I guess no one is going to apply this, so I did.
> > > >
> > > > If your patches don't get applied, please chase the maintainers (Jassi)
> > > > to apply them.
> > >
> > >
> > > This or it is an effect of known problem with mailbox and interconnect
> > > subsystems - maintainers never send notifications of applied patches
> > > (neither publicly nor privately like Greg does), so you will never know
> > > if anything gets applied.
> > >
> > > This as well could be in the next silently (wasn't in 15th Jan, though).
> >
> > Further investigation finds Jassi did apply this and 3 other patches.
> > Stephen reported a conflict on 1/6 with another Qcom patch
> > (conflicting with Bjorn's tree). No reply to Stephen, but *all* the
> > mbox binding patches were dropped.
> >
> > Here's what was dropped:
> >
> > f8f632c18c32 dt-bindings: mbox: add pic64gx mailbox compatibility to
> > mpfs mailbox
> > 945dc11a38a0 dt-bindings: mailbox: qcom: Add CPUCP mailbox controller
> > bindings for Kaanapali
> > 66b6e5daa915 dt-bindings: mailbox: qcom: Add IPCC support for
> > Kaanapali and Glymur Platforms
> > 9a92e22740e6 dt-bindings: mailbox: mediatek,mt8196-vcp-mbox: add mtk
> > vcp-mbox document
> >
> Yes, I had to reconstruct the mailbox for-next branch because some
> patch had an issue and the pr was not merged after a very late fix.
> Sorry I didn't realize people not receiving pick-confirmations was so
> problematic. I will make sure I reply to every patch that I pick.

TBC, the issue is not so much sending applied emails or not. It's the
not applying patches for 6 weeks (best I can tell, this patch was
never in next until after 12/10), and then dropping them silently.


Rob