[PATCH v4 0/5] Microchip mpfs/pic64gx pinctrl part 2

[PATCH v4 0/5] Microchip mpfs/pic64gx pinctrl part 2

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Hey Linus,

Rebased as requested, with the dts patch that snuck in dropped.

Cheers,
Conor.

changes in v4:
- rebase on devel
- drop dts patch

changes in v3:
- drop the todos
- rename the kconfig symbol
- move my drivers into a microchip dir
- use power-source instead of custom property

main changes in v2:
- bank voltage is now controllable from dt
- bank lockdown no longer controllable from dt
- dt_node_to_map callback is now a(n attempt at a) new generic function
- some schmitt properties now no longer supported

CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: linux-kernel@vger.kernel.org
CC: linux-gpio@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: Valentina.FernandezAlanis@microchip.com

Conor Dooley (5):
  pinctrl: move microchip riscv pinctrl drivers to a folder
  pinctrl: add generic functions + pins mapper
  dt-bindings: pinctrl: document polarfire soc mssio pin controller
  pinctrl: add polarfire soc mssio pinctrl driver
  MAINTAINERS: add Microchip mpfs mssio driver/bindings to entry

 .../pinctrl/microchip,mpfs-pinctrl-mssio.yaml | 109 +++
 .../microchip,mpfs-mss-top-sysreg.yaml        |   4 +
 MAINTAINERS                                   |   6 +-
 drivers/pinctrl/Kconfig                       |  23 +-
 drivers/pinctrl/Makefile                      |   4 +-
 drivers/pinctrl/microchip/Kconfig             |  17 +
 drivers/pinctrl/microchip/Makefile            |   5 +
 .../{ => microchip}/pinctrl-mpfs-iomux0.c     |   8 +-
 .../pinctrl/microchip/pinctrl-mpfs-mssio.c    | 737 ++++++++++++++++++
 .../{ => microchip}/pinctrl-pic64gx-gpio2.c   |   2 +-
 drivers/pinctrl/pinconf.h                     |  16 +
 drivers/pinctrl/pinctrl-generic.c             | 189 +++++
 12 files changed, 1095 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
 create mode 100644 drivers/pinctrl/microchip/Kconfig
 create mode 100644 drivers/pinctrl/microchip/Makefile
 rename drivers/pinctrl/{ => microchip}/pinctrl-mpfs-iomux0.c (98%)
 create mode 100644 drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
 rename drivers/pinctrl/{ => microchip}/pinctrl-pic64gx-gpio2.c (99%)
 create mode 100644 drivers/pinctrl/pinctrl-generic.c

-- 
2.51.0

[PATCH v4 1/5] pinctrl: move microchip riscv pinctrl drivers to a folder

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

There's three of these drivers now for the same platforms, move them
together with other microchip drivers to follow.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS                                     |  4 ++--
 drivers/pinctrl/Kconfig                         | 17 +----------------
 drivers/pinctrl/Makefile                        |  3 +--
 drivers/pinctrl/microchip/Kconfig               | 17 +++++++++++++++++
 drivers/pinctrl/microchip/Makefile              |  4 ++++
 .../{ => microchip}/pinctrl-mpfs-iomux0.c       |  8 ++++----
 .../{ => microchip}/pinctrl-pic64gx-gpio2.c     |  2 +-
 7 files changed, 30 insertions(+), 25 deletions(-)
 create mode 100644 drivers/pinctrl/microchip/Kconfig
 create mode 100644 drivers/pinctrl/microchip/Makefile
 rename drivers/pinctrl/{ => microchip}/pinctrl-mpfs-iomux0.c (98%)
 rename drivers/pinctrl/{ => microchip}/pinctrl-pic64gx-gpio2.c (99%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b11839cba9d..ff6084cb5797 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22472,8 +22472,8 @@ F:	drivers/gpio/gpio-mpfs.c
 F:	drivers/i2c/busses/i2c-microchip-corei2c.c
 F:	drivers/mailbox/mailbox-mpfs.c
 F:	drivers/pci/controller/plda/pcie-microchip-host.c
-F:	drivers/pinctrl/pinctrl-mpfs-iomux0.c
-F:	drivers/pinctrl/pinctrl-pic64gx-gpio2.c
+F:	drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
+F:	drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
 F:	drivers/pwm/pwm-microchip-core.c
 F:	drivers/reset/reset-mpfs.c
 F:	drivers/rtc/rtc-mpfs.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 0ea117581bde..d2a414450c16 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -486,14 +486,6 @@ config PINCTRL_PIC32MZDA
 	def_bool y if PIC32MZDA
 	select PINCTRL_PIC32
 
-config PINCTRL_PIC64GX
-	bool "pic64gx gpio2 pinctrl driver"
-	depends on ARCH_MICROCHIP || COMPILE_TEST
-	depends on OF
-	select GENERIC_PINCONF
-	help
-	  This selects the pinctrl driver for gpio2 on pic64gx.
-
 config PINCTRL_PISTACHIO
 	bool "IMG Pistachio SoC pinctrl driver"
 	depends on OF && (MIPS || COMPILE_TEST)
@@ -505,14 +497,6 @@ config PINCTRL_PISTACHIO
 	help
 	  This support pinctrl and GPIO driver for IMG Pistachio SoC.
 
-config PINCTRL_POLARFIRE_SOC
-	bool "Polarfire SoC pinctrl driver"
-	depends on ARCH_MICROCHIP || COMPILE_TEST
-	depends on OF
-	select GENERIC_PINCONF
-	help
-	  This selects the pinctrl driver for Microchip Polarfire SoC.
-
 config PINCTRL_RK805
 	tristate "Pinctrl and GPIO driver for RK805 PMIC"
 	depends on MFD_RK8XX
@@ -707,6 +691,7 @@ source "drivers/pinctrl/freescale/Kconfig"
 source "drivers/pinctrl/intel/Kconfig"
 source "drivers/pinctrl/mediatek/Kconfig"
 source "drivers/pinctrl/meson/Kconfig"
+source "drivers/pinctrl/microchip/Kconfig"
 source "drivers/pinctrl/mvebu/Kconfig"
 source "drivers/pinctrl/nomadik/Kconfig"
 source "drivers/pinctrl/nuvoton/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index be5200c23e60..05737b1afec9 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -48,9 +48,7 @@ obj-$(CONFIG_PINCTRL_OCELOT)	+= pinctrl-ocelot.o
 obj-$(CONFIG_PINCTRL_PALMAS)	+= pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_PEF2256)	+= pinctrl-pef2256.o
 obj-$(CONFIG_PINCTRL_PIC32)	+= pinctrl-pic32.o
-obj-$(CONFIG_PINCTRL_PIC64GX)	+= pinctrl-pic64gx-gpio2.o
 obj-$(CONFIG_PINCTRL_PISTACHIO)	+= pinctrl-pistachio.o
-obj-$(CONFIG_PINCTRL_POLARFIRE_SOC)	+= pinctrl-mpfs-iomux0.o
 obj-$(CONFIG_PINCTRL_RK805)	+= pinctrl-rk805.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_RP1)       += pinctrl-rp1.o
@@ -76,6 +74,7 @@ obj-y				+= freescale/
 obj-$(CONFIG_X86)		+= intel/
 obj-y				+= mediatek/
 obj-$(CONFIG_PINCTRL_MESON)	+= meson/
+obj-y				+= microchip/
 obj-y				+= mvebu/
 obj-y				+= nomadik/
 obj-y				+= nuvoton/
diff --git a/drivers/pinctrl/microchip/Kconfig b/drivers/pinctrl/microchip/Kconfig
new file mode 100644
index 000000000000..bdefe6541445
--- /dev/null
+++ b/drivers/pinctrl/microchip/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_PIC64GX
+	bool "pic64gx gpio2 pinctrl driver"
+	depends on ARCH_MICROCHIP || COMPILE_TEST
+	depends on OF
+	select GENERIC_PINCONF
+	help
+	  This selects the pinctrl driver for gpio2 on pic64gx.
+
+config PINCTRL_POLARFIRE_SOC
+	bool "Polarfire SoC pinctrl driver"
+	depends on ARCH_MICROCHIP || COMPILE_TEST
+	depends on OF
+	select GENERIC_PINCONF
+	help
+	  This selects the pinctrl driver for Microchip Polarfire SoC.
diff --git a/drivers/pinctrl/microchip/Makefile b/drivers/pinctrl/microchip/Makefile
new file mode 100644
index 000000000000..584d48e7be3b
--- /dev/null
+++ b/drivers/pinctrl/microchip/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_PINCTRL_PIC64GX)	+= pinctrl-pic64gx-gpio2.o
+obj-$(CONFIG_PINCTRL_POLARFIRE_SOC)	+= pinctrl-mpfs-iomux0.o
diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
similarity index 98%
rename from drivers/pinctrl/pinctrl-mpfs-iomux0.c
rename to drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
index cf5b2e4e8f5b..1b060a038920 100644
--- a/drivers/pinctrl/pinctrl-mpfs-iomux0.c
+++ b/drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
@@ -15,10 +15,10 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 
-#include "core.h"
-#include "pinctrl-utils.h"
-#include "pinconf.h"
-#include "pinmux.h"
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
 
 #define MPFS_IOMUX0_REG 0x200
 
diff --git a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
similarity index 99%
rename from drivers/pinctrl/pinctrl-pic64gx-gpio2.c
rename to drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
index f322bb5e6181..a0b3e839cf3b 100644
--- a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c
+++ b/drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
@@ -14,7 +14,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 
-#include "pinctrl-utils.h"
+#include "../pinctrl-utils.h"
 
 #define PIC64GX_PINMUX_REG 0x0
 
-- 
2.51.0

[PATCH v4 2/5] pinctrl: add generic functions + pins mapper

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Add a generic function to allow creation of groups and functions at
runtime based on devicetree content, before setting up mux mappings.
It works similarly to pinconf_generic_dt_node_to_map(), and
therefore parses pinconf properties and maps those too, allowing it
to be used as the dt_node_to_map member of the pinctrl_ops struct.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/pinctrl/Kconfig           |   6 +
 drivers/pinctrl/Makefile          |   1 +
 drivers/pinctrl/pinconf.h         |  16 +++
 drivers/pinctrl/pinctrl-generic.c | 189 ++++++++++++++++++++++++++++++
 4 files changed, 212 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-generic.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d2a414450c16..6cc5e214f4f3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -25,6 +25,12 @@ config GENERIC_PINCONF
 	bool
 	select PINCONF
 
+config GENERIC_PINCTRL
+	bool
+	depends on GENERIC_PINCONF
+	depends on GENERIC_PINCTRL_GROUPS
+	depends on GENERIC_PINMUX_FUNCTIONS
+
 config DEBUG_PINCTRL
 	bool "Debug PINCTRL calls"
 	depends on DEBUG_KERNEL
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 05737b1afec9..f7d5d5f76d0c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -7,6 +7,7 @@ obj-y				+= core.o pinctrl-utils.o
 obj-$(CONFIG_PINMUX)		+= pinmux.o
 obj-$(CONFIG_PINCONF)		+= pinconf.o
 obj-$(CONFIG_GENERIC_PINCONF)	+= pinconf-generic.o
+obj-$(CONFIG_GENERIC_PINCTRL)	+= pinctrl-generic.o
 obj-$(CONFIG_OF)		+= devicetree.o
 
 obj-$(CONFIG_PINCTRL_AMD)	+= pinctrl-amd.o
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index e1ae71610526..2880adef476e 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -160,3 +160,19 @@ pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev,
 	return -ENOTSUPP;
 }
 #endif
+
+#if defined(CONFIG_GENERIC_PINCTRL) && defined (CONFIG_OF)
+int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
+						 struct device_node *np,
+						 struct pinctrl_map **maps,
+						 unsigned int *num_maps);
+#else
+static inline int
+pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
+					     struct device_node *np,
+					     struct pinctrl_map **maps,
+					     unsigned int *num_maps)
+{
+	return -ENOTSUPP;
+}
+#endif
diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
new file mode 100644
index 000000000000..efb39c6a6703
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-generic.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "generic pinconfig core: " fmt
+
+#include <linux/array_size.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+#include "pinmux.h"
+
+static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+							   struct device_node *parent,
+							   struct device_node *np,
+							   struct pinctrl_map **maps,
+							   unsigned int *num_maps,
+							   unsigned int *num_reserved_maps,
+							   const char **group_names,
+							   unsigned int ngroups)
+{
+	struct device *dev = pctldev->dev;
+	const char **functions;
+	const char *group_name;
+	unsigned long *configs;
+	unsigned int num_configs, pin, *pins;
+	int npins, ret, reserve = 1;
+
+	npins = of_property_count_u32_elems(np, "pins");
+
+	if (npins < 1) {
+		dev_err(dev, "invalid pinctrl group %pOFn.%pOFn %d\n",
+			parent, np, npins);
+		return npins;
+	}
+
+	group_name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", parent, np);
+	if (!group_name)
+		return -ENOMEM;
+
+	group_names[ngroups] = group_name;
+
+	pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
+	if (!pins)
+		return -ENOMEM;
+
+	functions = devm_kcalloc(dev, npins, sizeof(*functions), GFP_KERNEL);
+	if (!functions)
+		return -ENOMEM;
+
+	for (int i = 0; i < npins; i++) {
+		ret = of_property_read_u32_index(np, "pins", i, &pin);
+		if (ret)
+			return ret;
+
+		pins[i] = pin;
+
+		ret = of_property_read_string(np, "function", &functions[i]);
+		if (ret)
+			return ret;
+	}
+
+	ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);
+	if (ret)
+		return ret;
+
+	ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name,
+					parent->name);
+	if (ret < 0)
+		return ret;
+
+	ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, functions);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "failed to add group %s: %d\n",
+				     group_name, ret);
+
+	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n",
+			group_name);
+
+	if (num_configs == 0)
+		return 0;
+
+	ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);
+	if (ret)
+		return ret;
+
+	ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name,
+					    configs,
+			num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
+	kfree(configs);
+	if (ret)
+		return ret;
+
+	return 0;
+};
+
+/*
+ * For platforms that do not define groups or functions in the driver, but
+ * instead use the devicetree to describe them. This function will, unlike
+ * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups
+ * and functions, create them in addition to parsing pinconf properties and
+ * adding mappings.
+ */
+int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
+						 struct device_node *np,
+						 struct pinctrl_map **maps,
+						 unsigned int *num_maps)
+{
+	struct device *dev = pctldev->dev;
+	struct device_node *child_np;
+	const char **group_names;
+	unsigned int num_reserved_maps = 0;
+	int ngroups = 0;
+	int ret;
+
+	*maps = NULL;
+	*num_maps = 0;
+
+	/*
+	 * Check if this is actually the pins node, or a parent containing
+	 * multiple pins nodes.
+	 */
+	if (!of_property_present(np, "pins"))
+		goto parent;
+
+	group_names = devm_kcalloc(dev, 1, sizeof(*group_names), GFP_KERNEL);
+	if (!group_names)
+		return -ENOMEM;
+
+	ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, np,
+							      maps, num_maps,
+							      &num_reserved_maps,
+							      group_names,
+							      ngroups);
+	if (ret) {
+		pinctrl_utils_free_map(pctldev, *maps, *num_maps);
+		return dev_err_probe(dev, ret, "error figuring out mappings for %s\n", np->name);
+	}
+
+	ret = pinmux_generic_add_function(pctldev, np->name, group_names, 1, NULL);
+	if (ret < 0) {
+		pinctrl_utils_free_map(pctldev, *maps, *num_maps);
+		return dev_err_probe(dev, ret, "error adding function %s\n", np->name);
+	}
+
+	return 0;
+
+parent:
+	for_each_available_child_of_node(np, child_np)
+		ngroups += 1;
+
+	group_names = devm_kcalloc(dev, ngroups, sizeof(*group_names), GFP_KERNEL);
+	if (!group_names)
+		return -ENOMEM;
+
+	ngroups = 0;
+	for_each_available_child_of_node_scoped(np, child_np) {
+		ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, child_np,
+								      maps, num_maps,
+								      &num_reserved_maps,
+								      group_names,
+								      ngroups);
+		if (ret) {
+			pinctrl_utils_free_map(pctldev, *maps, *num_maps);
+			return dev_err_probe(dev, ret, "error figuring out mappings for %s\n",
+					     np->name);
+		}
+
+		ngroups++;
+	}
+
+	ret = pinmux_generic_add_function(pctldev, np->name, group_names, ngroups, NULL);
+	if (ret < 0) {
+		pinctrl_utils_free_map(pctldev, *maps, *num_maps);
+		return dev_err_probe(dev, ret, "error adding function %s\n", np->name);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pinctrl_generic_pins_function_dt_node_to_map);
-- 
2.51.0

[PATCH v4 3/5] dt-bindings: pinctrl: document polarfire soc mssio pin controller

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the
Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6,
which determine what function in routed to them, and
MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin.

Document it, including several custom configuration options that stem
from MSS Configurator options (the MSS Configurator is part of the FPGA
tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping
with an MSS Configurator option, unlike clamp-diode or lockdown, and I
do not know the effect of any bits in the field. I have no been able to
find an explanation for these bits in documentation.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../pinctrl/microchip,mpfs-pinctrl-mssio.yaml | 109 ++++++++++++++++++
 .../microchip,mpfs-mss-top-sysreg.yaml        |   4 +
 2 files changed, 113 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
new file mode 100644
index 000000000000..fe05196160f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Polarfire SoC MSSIO pinctrl
+
+maintainers:
+  - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+  compatible:
+    oneOf:
+      - const: microchip,mpfs-pinctrl-mssio
+      - items:
+          - const: microchip,pic64gx-pinctrl-mssio
+          - const: microchip,mpfs-pinctrl-mssio
+
+  reg:
+    maxItems: 1
+
+  pinctrl-use-default: true
+
+patternProperties:
+  '-cfg$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '-pins$':
+        type: object
+        additionalProperties: false
+
+        allOf:
+          - $ref: pincfg-node.yaml#
+          - $ref: pinmux-node.yaml#
+
+        properties:
+          pins:
+            description:
+              The list of IOs that properties in the pincfg node apply to.
+
+          function:
+            description:
+              A string containing the name of the function to mux for these
+              pins. The "reserved" function tristates a pin.
+            enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc
+                    reserved, gpio, fabric-test, tied-low, tied-high, tristate ]
+
+          bias-bus-hold: true
+          bias-disable: true
+          bias-pull-down: true
+          bias-pull-up: true
+          input-schmitt-enable: true
+          low-power-enable: true
+
+          drive-strength:
+            enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ]
+
+          power-source:
+            description:
+              Which bank voltage to use. This cannot differ for pins in a
+              given bank, the whole bank uses the same voltage.
+            enum: [ 1200000, 1500000, 1800000, 2500000, 3300000 ]
+
+          microchip,clamp-diode:
+            $ref: /schemas/types.yaml#/definitions/flag
+            description:
+              Reflects the "Clamp Diode" setting in the MSS Configurator for
+              this pin. This setting controls whether or not input voltage
+              clamping should be enabled.
+
+          microchip,ibufmd:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            default: 0
+            description:
+              Reflects the "IBUFMD" bits in the MSS Configurator output files
+              for this pin.
+
+        required:
+          - pins
+          - function
+          - power-source
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    pinctrl@204 {
+      compatible = "microchip,mpfs-pinctrl-mssio";
+      reg = <0x204 0x7c>;
+
+      ikrd-spi1-cfg {
+        spi1-pins {
+          pins = <30>, <31>, <32>, <33>;
+          function = "spi";
+          bias-pull-up;
+          drive-strength = <8>;
+          power-source = <3300000>;
+          microchip,ibufmd = <0x1>;
+        };
+      };
+    };
+...
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
index 39987f722411..44e4a50c3155 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
@@ -42,6 +42,10 @@ properties:
     type: object
     $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
 
+  pinctrl@204:
+    type: object
+    $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
+
 required:
   - compatible
   - reg
-- 
2.51.0

[PATCH v4 4/5] pinctrl: add polarfire soc mssio pinctrl driver

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the
Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6,
which determine what function in routed to them, and
MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin.

Add a driver for this pin controller, including several custom
properties that reflect aspects of the MSS's configuration.

Reuse the Kconfig option for iomux0, since controlling MSSIOs without
iomux0 routing a function to the MSSIOs in question is pointless, and
routing a function to the MSSIOs is equally unhelpful if none of them
are configured to make use of that function.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/pinctrl/microchip/Kconfig             |   6 +-
 drivers/pinctrl/microchip/Makefile            |   1 +
 .../pinctrl/microchip/pinctrl-mpfs-mssio.c    | 737 ++++++++++++++++++
 3 files changed, 741 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

diff --git a/drivers/pinctrl/microchip/Kconfig b/drivers/pinctrl/microchip/Kconfig
index bdefe6541445..e8bc01946324 100644
--- a/drivers/pinctrl/microchip/Kconfig
+++ b/drivers/pinctrl/microchip/Kconfig
@@ -9,9 +9,9 @@ config PINCTRL_PIC64GX
 	  This selects the pinctrl driver for gpio2 on pic64gx.
 
 config PINCTRL_POLARFIRE_SOC
-	bool "Polarfire SoC pinctrl driver"
+	bool "Polarfire SoC pinctrl drivers"
 	depends on ARCH_MICROCHIP || COMPILE_TEST
 	depends on OF
-	select GENERIC_PINCONF
+	select GENERIC_PINCTRL
 	help
-	  This selects the pinctrl driver for Microchip Polarfire SoC.
+	  This selects the pinctrl drivers for Microchip Polarfire SoC.
diff --git a/drivers/pinctrl/microchip/Makefile b/drivers/pinctrl/microchip/Makefile
index 584d48e7be3b..ab0575cd2ed1 100644
--- a/drivers/pinctrl/microchip/Makefile
+++ b/drivers/pinctrl/microchip/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_PINCTRL_PIC64GX)	+= pinctrl-pic64gx-gpio2.o
 obj-$(CONFIG_PINCTRL_POLARFIRE_SOC)	+= pinctrl-mpfs-iomux0.o
+obj-$(CONFIG_PINCTRL_POLARFIRE_SOC)	+= pinctrl-mpfs-mssio.o
diff --git a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
new file mode 100644
index 000000000000..3d5ffd6cb14b
--- /dev/null
+++ b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
@@ -0,0 +1,737 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/seq_file.h>
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+#define MPFS_PINCTRL_PAD_MUX_MASK GENMASK(3, 0)
+
+#define MPFS_PINCTRL_IOCFG_MASK GENMASK(14, 0)
+#define MPFS_PINCTRL_IBUFMD_MASK GENMASK(2, 0)
+#define MPFS_PINCTRL_DRV_MASK GENMASK(6, 3)
+#define MPFS_PINCTRL_CLAMP BIT(7)
+#define MPFS_PINCTRL_ENHYST BIT(8)
+#define MPFS_PINCTRL_LOCKDN BIT(9)
+#define MPFS_PINCTRL_WPD BIT(10)
+#define MPFS_PINCTRL_WPU BIT(11)
+#define MPFS_PINCTRL_PULL_MASK GENMASK(11, 10)
+#define MPFS_PINCTRL_LP_PERSIST_EN BIT(12)
+#define MPFS_PINCTRL_LP_BYPASS_EN BIT(13)
+
+#define MPFS_PINCTRL_MSSIO_BANK2_CFG_CR 0x1c4
+#define MPFS_PINCTRL_MSSIO_BANK4_CFG_CR 0x1c8
+#define MPFS_PINCTRL_BANK_VOLTAGE_MASK GENMASK(19, 16)
+
+#define MPFS_PINCTRL_IOCFG01_REG 0x234
+
+#define MPFS_PINCTRL_INTER_BANK_GAP 0x4
+
+#define MPFS_PINCTRL_BANK2_START 14
+
+#define MPFS_PINCTRL_LOCKDOWN (PIN_CONFIG_END + 1)
+#define MPFS_PINCTRL_CLAMP_DIODE (PIN_CONFIG_END + 2)
+#define MPFS_PINCTRL_IBUFMD (PIN_CONFIG_END + 3)
+
+struct mpfs_pinctrl_mux_config {
+	u8 pin;
+	u8 function;
+};
+
+struct mpfs_pinctrl {
+	struct pinctrl_dev *pctrl;
+	struct device *dev;
+	struct regmap *regmap;
+	struct regmap *sysreg_regmap;
+	struct mutex mutex;
+	struct pinctrl_desc desc;
+};
+
+struct mpfs_pinctrl_drive_strength {
+	u8 ma;
+	u8 val;
+};
+
+struct mpfs_pinctrl_bank_voltage {
+	u32 uv;
+	u8 val;
+};
+
+static struct mpfs_pinctrl_drive_strength mpfs_pinctrl_drive_strengths[8] = {
+	{ .ma = 2, .val = 2 },
+	{ .ma = 4, .val = 3 },
+	{ .ma = 6, .val = 4 },
+	{ .ma = 8, .val = 5 },
+	{ .ma = 10, .val = 6 },
+	{ .ma = 12, .val = 7 },
+	{ .ma = 16, .val = 10 },
+	{ .ma = 20, .val = 12 },
+};
+static struct mpfs_pinctrl_bank_voltage mpfs_pinctrl_bank_voltages[8] = {
+	{ .uv = 1200000, .val = 0 },
+	{ .uv = 1500000, .val = 2 },
+	{ .uv = 1800000, .val = 4 },
+	{ .uv = 2500000, .val = 6 },
+	{ .uv = 3300000, .val = 8 },
+	{ .uv = 0, .val = 0x3f }, // pin unused
+};
+
+static int mpfs_pinctrl_get_drive_strength_ma(u32 drive_strength)
+{
+	size_t num = ARRAY_SIZE(mpfs_pinctrl_drive_strengths);
+
+	for (int i = 0; i < num; i++)
+		if (drive_strength == mpfs_pinctrl_drive_strengths[i].val)
+			return mpfs_pinctrl_drive_strengths[i].ma;
+
+	return -EINVAL;
+}
+
+static int mpfs_pinctrl_get_drive_strength_val(u32 drive_strength_ma)
+{
+	size_t num = ARRAY_SIZE(mpfs_pinctrl_drive_strengths);
+
+	if (!drive_strength_ma)
+		return -EINVAL;
+
+	for (int i = 0; i < num; i++)
+		if (drive_strength_ma <= mpfs_pinctrl_drive_strengths[i].ma)
+			return mpfs_pinctrl_drive_strengths[i].val;
+
+	return mpfs_pinctrl_drive_strengths[num - 1].val;
+}
+
+static int mpfs_pinctrl_get_bank_voltage_uv(u32 bank_voltage)
+{
+	size_t num = ARRAY_SIZE(mpfs_pinctrl_bank_voltages);
+
+	for (int i = 0; i < num; i++)
+		if (bank_voltage == mpfs_pinctrl_bank_voltages[i].val)
+			return mpfs_pinctrl_bank_voltages[i].uv;
+
+	return -EINVAL;
+}
+
+static int mpfs_pinctrl_get_bank_voltage_val(u32 bank_voltage_uv)
+{
+	size_t num = ARRAY_SIZE(mpfs_pinctrl_bank_voltages);
+
+	for (int i = 0; i < num; i++)
+		if (bank_voltage_uv <= mpfs_pinctrl_bank_voltages[i].uv)
+			return mpfs_pinctrl_bank_voltages[i].val;
+
+	return -EINVAL;
+}
+
+static u32 mpfs_pinctrl_pin_to_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned int pin)
+{
+	u32 bank_voltage, val;
+
+	if (pin < MPFS_PINCTRL_BANK2_START)
+		regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR, &val);
+	else
+		regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR, &val);
+
+	bank_voltage = FIELD_GET(MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
+
+	return mpfs_pinctrl_get_bank_voltage_uv(bank_voltage);
+}
+
+static void mpfs_pinctrl_set_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned int pin,
+					  u32 bank_voltage)
+{
+	u32 val = FIELD_PREP(MPFS_PINCTRL_BANK_VOLTAGE_MASK, bank_voltage);
+
+	if (pin < MPFS_PINCTRL_BANK2_START)
+		regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR,
+				   MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
+	else
+		regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR,
+				   MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
+}
+
+static char *mpfs_pinctrl_function_names[] = {
+	"sd",
+	"emmc",
+	"qspi",
+	"spi",
+	"usb",
+	"uart",
+	"i2c",
+	"can",
+	"mdio",
+	"misc",
+	"reserved",
+	"gpio",
+	"fabric test",
+	"tied-low",
+	"tied-high",
+	"tristate"
+};
+
+static int mpfs_pinctrl_function_map(const char *function)
+{
+	size_t num = ARRAY_SIZE(mpfs_pinctrl_function_names);
+
+	for (int i = 0; i < num; i++)
+		if (!strcmp(function, mpfs_pinctrl_function_names[i]))
+			return i;
+
+	return -EINVAL;
+}
+
+static const struct pinconf_generic_params mpfs_pinctrl_custom_bindings[] = {
+	{ "microchip,clamp-diode", MPFS_PINCTRL_CLAMP_DIODE, 1 },
+	{ "microchip,ibufmd", MPFS_PINCTRL_IBUFMD, 0x0 },
+};
+
+static int mpfs_pinctrl_pin_to_iomux_offset(unsigned int pin)
+{
+	int offset;
+
+	switch (pin) {
+	case 0 ... 7:
+		offset = pin * 4;
+		break;
+	case 8 ... 13:
+		offset = (pin - 8) * 4;
+		break;
+	case 14 ... 21:
+		offset = (pin - 14) * 4;
+		break;
+	case 22 ... 29:
+		offset = (pin - 22) * 4;
+		break;
+	case 30 ... 37:
+		offset = (pin - 30) * 4;
+		break;
+	default:
+		offset = -EINVAL;
+	}
+
+	return offset;
+}
+
+static int mpfs_pinctrl_pin_to_iomux_reg(unsigned int pin)
+{
+	int reg;
+
+	switch (pin) {
+	case 0 ... 7:
+		reg = 0x204;
+		break;
+	case 8 ... 13:
+		reg = 0x208;
+		break;
+	case 14 ... 21:
+		reg = 0x20c;
+		break;
+	case 22 ... 29:
+		reg = 0x210;
+		break;
+	case 30 ... 37:
+		reg = 0x214;
+		break;
+	default:
+		reg = -EINVAL;
+	}
+
+	return reg;
+}
+
+static int mpfs_pinctrl_pin_to_iocfg_reg(unsigned int pin)
+{
+	u32 reg = MPFS_PINCTRL_IOCFG01_REG;
+
+	if (pin >= MPFS_PINCTRL_BANK2_START)
+		reg += MPFS_PINCTRL_INTER_BANK_GAP;
+
+	// 2 pins per 32-bit register
+	reg += (pin / 2) * 0x4;
+
+	return reg;
+}
+
+static int mpfs_pinctrl_pin_to_iocfg_offset(unsigned int pin)
+{
+	return 16 * (pin % 2);
+}
+
+static void mpfs_pinctrl_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
+				  unsigned int pin)
+{
+	struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+	u32 func;
+	int reg, offset;
+
+	reg = mpfs_pinctrl_pin_to_iomux_reg(pin);
+	offset = mpfs_pinctrl_pin_to_iomux_offset(pin);
+
+	seq_printf(seq, "reg: %x, offset: %u ", reg, offset);
+	seq_printf(seq, "pin: %u ", pin);
+
+	if (reg < 0 || offset < 0)
+		return;
+
+	regmap_read(pctrl->regmap, reg, &func);
+	func = (func >> offset) & MPFS_PINCTRL_PAD_MUX_MASK;
+	seq_printf(seq, "func: %s (%x)\n", mpfs_pinctrl_function_names[func], func);
+}
+
+static const struct pinctrl_ops mpfs_pinctrl_ops = {
+	.get_groups_count = pinctrl_generic_get_group_count,
+	.get_group_name	= pinctrl_generic_get_group_name,
+	.get_group_pins	= pinctrl_generic_get_group_pins,
+	.pin_dbg_show = mpfs_pinctrl_dbg_show,
+	.dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map,
+	.dt_free_map = pinctrl_utils_free_map,
+};
+
+static int mpfs_pinctrl_set_pin_func(struct mpfs_pinctrl *pctrl, u8 pin, u8 function)
+{
+	struct device *dev = pctrl->dev;
+	int reg, offset;
+	u32 func, mask;
+
+	reg = mpfs_pinctrl_pin_to_iomux_reg(pin);
+	offset = mpfs_pinctrl_pin_to_iomux_offset(pin);
+
+	func = function << offset;
+	mask = MPFS_PINCTRL_PAD_MUX_MASK << offset;
+
+	dev_dbg(dev, "Setting pin %u. reg: %x offset %u func %x\n", pin, reg, offset, func);
+
+	if (reg < 0 || offset < 0)
+		return -EINVAL;
+
+	regmap_update_bits(pctrl->regmap, reg, mask, func);
+
+	return 0;
+}
+
+static int mpfs_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
+				unsigned int gsel)
+{
+	struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+	const struct group_desc *group;
+	const char **functions;
+
+	group = pinctrl_generic_get_group(pctrl_dev, gsel);
+	if (!group)
+		return -EINVAL;
+
+	functions = group->data;
+
+	for (int i = 0; i < group->grp.npins; i++) {
+		int function;
+
+		function = mpfs_pinctrl_function_map(functions[i]);
+		if (function < 0) {
+			dev_err(pctrl->dev, "invalid function %s\n", functions[i]);
+			return function;
+		}
+
+		mpfs_pinctrl_set_pin_func(pctrl, group->grp.pins[i], function);
+	}
+
+	return 0;
+}
+
+static const struct pinmux_ops mpfs_pinctrl_pinmux_ops = {
+	.get_functions_count	= pinmux_generic_get_function_count,
+	.get_function_name	= pinmux_generic_get_function_name,
+	.get_function_groups	= pinmux_generic_get_function_groups,
+	.set_mux		= mpfs_pinctrl_set_mux,
+};
+
+static int mpfs_pinctrl_pinconf_get(struct pinctrl_dev *pctrl_dev, unsigned int pin,
+				    unsigned long *config)
+{
+	struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+	int param = pinconf_to_config_param(*config);
+	int reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
+	int val;
+	u32 arg;
+	u8 str;
+
+	regmap_read(pctrl->regmap, reg, &val);
+
+	val = val >> mpfs_pinctrl_pin_to_iocfg_offset(pin);
+	val = val & MPFS_PINCTRL_IOCFG_MASK;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_BUS_HOLD:
+		if (!(val & MPFS_PINCTRL_WPD))
+			return -EINVAL;
+
+		if (!(val & MPFS_PINCTRL_WPU))
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		if (!(val & MPFS_PINCTRL_WPD))
+			return -EINVAL;
+
+		if (val & MPFS_PINCTRL_WPU)
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		if (!(val & MPFS_PINCTRL_WPU))
+			return -EINVAL;
+
+		if (val & MPFS_PINCTRL_WPD)
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_BIAS_DISABLE:
+		if (val & MPFS_PINCTRL_PULL_MASK)
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		str = FIELD_GET(MPFS_PINCTRL_DRV_MASK, val);
+		if (!str)
+			return -EINVAL;
+
+		arg = mpfs_pinctrl_get_drive_strength_ma(str);
+		break;
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		if (!FIELD_GET(MPFS_PINCTRL_ENHYST, val))
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_PERSIST_STATE:
+		if (!FIELD_GET(MPFS_PINCTRL_LP_PERSIST_EN, val))
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_MODE_LOW_POWER:
+		if (!FIELD_GET(MPFS_PINCTRL_LP_BYPASS_EN, val))
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case PIN_CONFIG_POWER_SOURCE:
+		arg = mpfs_pinctrl_pin_to_bank_voltage(pctrl, pin);
+		break;
+	case MPFS_PINCTRL_CLAMP_DIODE:
+		if (!FIELD_GET(MPFS_PINCTRL_CLAMP, val))
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case MPFS_PINCTRL_LOCKDOWN:
+		/*
+		 * Lockdown is a read-only configuration, it'll get set if the
+		 * tamper unit triggers global lockdown and lockdown has been
+		 * set in the MSS Configurator for the bank a pin belongs to.
+		 */
+		if (!FIELD_GET(MPFS_PINCTRL_LOCKDN, val))
+			return -EINVAL;
+
+		arg = 1;
+		break;
+	case MPFS_PINCTRL_IBUFMD:
+		arg = FIELD_GET(MPFS_PINCTRL_IBUFMD_MASK, val);
+		break;
+	default:
+		return -ENOTSUPP;
+	}
+
+	*config = pinconf_to_config_packed(param, arg);
+
+	return 0;
+}
+
+static int mpfs_pinctrl_pinconf_generate_config(struct mpfs_pinctrl *pctrl, unsigned int pin,
+						unsigned long *configs, unsigned int num_configs,
+						u32 *value, u32 *bank_voltage)
+{
+	u32 val = 0;
+
+	for (int i = 0; i < num_configs; i++) {
+		int param, tmp;
+		u32 arg;
+
+		param = pinconf_to_config_param(configs[i]);
+		arg = pinconf_to_config_argument(configs[i]);
+
+		switch (param) {
+		case PIN_CONFIG_BIAS_BUS_HOLD:
+			val |= MPFS_PINCTRL_PULL_MASK;
+			break;
+		case PIN_CONFIG_BIAS_PULL_DOWN:
+			val &= ~MPFS_PINCTRL_PULL_MASK;
+			val |= MPFS_PINCTRL_WPD;
+			break;
+		case PIN_CONFIG_BIAS_PULL_UP:
+			val &= ~MPFS_PINCTRL_PULL_MASK;
+			val |= MPFS_PINCTRL_WPU;
+			break;
+		case PIN_CONFIG_BIAS_DISABLE:
+			val &= ~MPFS_PINCTRL_PULL_MASK;
+			break;
+		case PIN_CONFIG_DRIVE_STRENGTH:
+			tmp = mpfs_pinctrl_get_drive_strength_val(arg);
+			if (tmp < 0)
+				return tmp;
+
+			val |= FIELD_PREP(MPFS_PINCTRL_DRV_MASK, tmp);
+			break;
+		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+			if (!arg)
+				break;
+			val |= MPFS_PINCTRL_ENHYST;
+			break;
+		case PIN_CONFIG_PERSIST_STATE:
+			val |= MPFS_PINCTRL_LP_PERSIST_EN;
+			break;
+		case PIN_CONFIG_MODE_LOW_POWER:
+			if (arg)
+				val |= MPFS_PINCTRL_LP_BYPASS_EN;
+			break;
+		case PIN_CONFIG_POWER_SOURCE:
+			tmp = mpfs_pinctrl_get_bank_voltage_val(arg);
+			if (tmp < 0)
+				return tmp;
+
+			*bank_voltage = tmp;
+			break;
+		case MPFS_PINCTRL_CLAMP_DIODE:
+			val |= MPFS_PINCTRL_CLAMP;
+			break;
+		case MPFS_PINCTRL_IBUFMD:
+			val |= FIELD_PREP(MPFS_PINCTRL_IBUFMD_MASK, arg);
+			break;
+		default:
+			dev_err(pctrl->dev, "config %u not supported\n", param);
+			return -ENOTSUPP;
+		}
+	}
+
+	*value = val;
+	return 0;
+}
+
+static int mpfs_pinctrl_pin_set_config(struct mpfs_pinctrl *pctrl, unsigned int pin, u32 config)
+{
+	int reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
+	int offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
+	u32 val, mask;
+
+	mask = MPFS_PINCTRL_IOCFG_MASK << offset;
+	val = config << offset;
+
+	regmap_update_bits(pctrl->regmap, reg, mask, val);
+
+	return 0;
+}
+
+static int mpfs_pinctrl_pinconf_set(struct pinctrl_dev *pctrl_dev, unsigned int pin,
+				    unsigned long *configs, unsigned int num_configs)
+{
+	struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+	u32 val, bank_voltage = 0;
+	int ret;
+
+	ret = mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_configs, &val,
+						   &bank_voltage);
+	if (ret)
+		return ret;
+
+	ret = mpfs_pinctrl_pin_set_config(pctrl, pin, val);
+	if (ret)
+		return ret;
+
+	if (bank_voltage)
+		mpfs_pinctrl_set_bank_voltage(pctrl, pin, bank_voltage);
+
+	return 0;
+}
+
+static int mpfs_pinctrl_pinconf_group_set(struct pinctrl_dev *pctrl_dev, unsigned int gsel,
+					  unsigned long *configs, unsigned int num_configs)
+{
+	struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+	const struct group_desc *group;
+	unsigned int pin;
+	u32 val, bank_voltage = 0;
+	int ret;
+
+	group = pinctrl_generic_get_group(pctrl_dev, gsel);
+	if (!group)
+		return -EINVAL;
+
+	/*
+	 * Assume that the first pin in a group is representative, as the mss
+	 * configurator doesn't allow splitting a function between two banks.
+	 */
+	pin = group->grp.pins[0];
+
+	ret = mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_configs, &val,
+						   &bank_voltage);
+	if (ret)
+		return ret;
+
+	for (int i = 0; i < group->grp.npins; i++)
+		mpfs_pinctrl_pin_set_config(pctrl, group->grp.pins[i], val);
+
+	if (bank_voltage)
+		mpfs_pinctrl_set_bank_voltage(pctrl, group->grp.pins[0], bank_voltage);
+
+	return 0;
+}
+
+static void mpfs_pinctrl_pinconf_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
+					  unsigned int pin)
+{
+	struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+	u32 val;
+	int reg, offset;
+
+	reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
+	offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
+
+	seq_printf(seq, "pin: %u ", pin);
+	seq_printf(seq, "reg: %x offset: %u ", reg, offset);
+
+	if (reg < 0 || offset < 0)
+		return;
+
+	regmap_read(pctrl->regmap, reg, &val);
+	val = (val & (MPFS_PINCTRL_IOCFG_MASK << offset)) >> offset;
+	seq_printf(seq, "val: %x\n", val);
+}
+
+static const struct pinconf_ops mpfs_pinctrl_pinconf_ops = {
+	.pin_config_get			= mpfs_pinctrl_pinconf_get,
+	.pin_config_set			= mpfs_pinctrl_pinconf_set,
+	.pin_config_group_set		= mpfs_pinctrl_pinconf_group_set,
+	.pin_config_dbg_show		= mpfs_pinctrl_pinconf_dbg_show,
+	.is_generic			= true,
+};
+
+static const struct pinctrl_pin_desc mpfs_pinctrl_pins[] = {
+	PINCTRL_PIN(0,  "bank 4 0"),
+	PINCTRL_PIN(1,  "bank 4 1"),
+	PINCTRL_PIN(2,  "bank 4 2"),
+	PINCTRL_PIN(3,  "bank 4 3"),
+	PINCTRL_PIN(4,  "bank 4 4"),
+	PINCTRL_PIN(5,  "bank 4 5"),
+	PINCTRL_PIN(6,  "bank 4 6"),
+	PINCTRL_PIN(7,  "bank 4 7"),
+	PINCTRL_PIN(8,  "bank 4 8"),
+	PINCTRL_PIN(9,  "bank 4 9"),
+	PINCTRL_PIN(10, "bank 4 10"),
+	PINCTRL_PIN(11, "bank 4 11"),
+	PINCTRL_PIN(12, "bank 4 12"),
+	PINCTRL_PIN(13, "bank 4 13"),
+
+	PINCTRL_PIN(14, "bank 2 0"),
+	PINCTRL_PIN(15, "bank 2 1"),
+	PINCTRL_PIN(16, "bank 2 2"),
+	PINCTRL_PIN(17, "bank 2 3"),
+	PINCTRL_PIN(18, "bank 2 4"),
+	PINCTRL_PIN(19, "bank 2 5"),
+	PINCTRL_PIN(20, "bank 2 6"),
+	PINCTRL_PIN(21, "bank 2 7"),
+	PINCTRL_PIN(22, "bank 2 8"),
+	PINCTRL_PIN(23, "bank 2 9"),
+	PINCTRL_PIN(24, "bank 2 10"),
+	PINCTRL_PIN(25, "bank 2 11"),
+	PINCTRL_PIN(26, "bank 2 12"),
+	PINCTRL_PIN(27, "bank 2 13"),
+	PINCTRL_PIN(28, "bank 2 14"),
+	PINCTRL_PIN(29, "bank 2 15"),
+	PINCTRL_PIN(30, "bank 2 16"),
+	PINCTRL_PIN(31, "bank 2 17"),
+	PINCTRL_PIN(32, "bank 2 18"),
+	PINCTRL_PIN(33, "bank 2 19"),
+	PINCTRL_PIN(34, "bank 2 20"),
+	PINCTRL_PIN(35, "bank 2 21"),
+	PINCTRL_PIN(36, "bank 2 22"),
+	PINCTRL_PIN(37, "bank 2 23"),
+};
+
+static int mpfs_pinctrl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mpfs_pinctrl *pctrl;
+	int ret;
+
+	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
+	if (!pctrl)
+		return -ENOMEM;
+
+	pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
+	if (IS_ERR(pctrl->regmap))
+		dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
+
+	pctrl->sysreg_regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-scb");
+	if (IS_ERR(pctrl->sysreg_regmap))
+		return PTR_ERR(pctrl->sysreg_regmap);
+
+	pctrl->desc.name = dev_name(dev);
+	pctrl->desc.pins = mpfs_pinctrl_pins;
+	pctrl->desc.npins = ARRAY_SIZE(mpfs_pinctrl_pins);
+	pctrl->desc.pctlops = &mpfs_pinctrl_ops;
+	pctrl->desc.pmxops = &mpfs_pinctrl_pinmux_ops;
+	pctrl->desc.confops = &mpfs_pinctrl_pinconf_ops;
+	pctrl->desc.owner = THIS_MODULE;
+	pctrl->desc.num_custom_params = ARRAY_SIZE(mpfs_pinctrl_custom_bindings);
+	pctrl->desc.custom_params = mpfs_pinctrl_custom_bindings;
+
+	pctrl->dev = dev;
+
+	ret = devm_mutex_init(dev, &pctrl->mutex);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, pctrl);
+
+	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
+	if (IS_ERR(pctrl->pctrl))
+		return PTR_ERR(pctrl->pctrl);
+
+	return 0;
+}
+
+static const struct of_device_id mpfs_pinctrl_of_match[] = {
+	{ .compatible = "microchip,mpfs-pinctrl-mssio" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, mpfs_pinctrl_of_match);
+
+static struct platform_driver mpfs_pinctrl_driver = {
+	.driver = {
+		.name = "mpfs-pinctrl",
+		.of_match_table = mpfs_pinctrl_of_match,
+	},
+	.probe = mpfs_pinctrl_probe,
+};
+module_platform_driver(mpfs_pinctrl_driver);
+
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("Polarfire SoC mssio pinctrl driver");
+MODULE_LICENSE("GPL");
-- 
2.51.0

[PATCH v4 5/5] MAINTAINERS: add Microchip mpfs mssio driver/bindings to entry

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Add the new mssio driver and bindings to the existing entry
for Microchip RISC-V devices.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ff6084cb5797..0cb24094aa1a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22458,6 +22458,7 @@ F:	Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
 F:	Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
 F:	Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
 F:	Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
+F:	Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
 F:	Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
 F:	Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
 F:	Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -22473,6 +22474,7 @@ F:	drivers/i2c/busses/i2c-microchip-corei2c.c
 F:	drivers/mailbox/mailbox-mpfs.c
 F:	drivers/pci/controller/plda/pcie-microchip-host.c
 F:	drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
+F:	drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
 F:	drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
 F:	drivers/pwm/pwm-microchip-core.c
 F:	drivers/reset/reset-mpfs.c
-- 
2.51.0

Re: [PATCH v4 3/5] dt-bindings: pinctrl: document polarfire soc mssio pin controller

[Rob Herring (Arm)]

On Tue, 20 Jan 2026 18:15:41 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the
> Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6,
> which determine what function in routed to them, and
> MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin.
> 
> Document it, including several custom configuration options that stem
> from MSS Configurator options (the MSS Configurator is part of the FPGA
> tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping
> with an MSS Configurator option, unlike clamp-diode or lockdown, and I
> do not know the effect of any bits in the field. I have no been able to
> find an explanation for these bits in documentation.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../pinctrl/microchip,mpfs-pinctrl-mssio.yaml | 109 ++++++++++++++++++
>  .../microchip,mpfs-mss-top-sysreg.yaml        |   4 +
>  2 files changed, 113 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v4 0/5] Microchip mpfs/pic64gx pinctrl part 2

[Linus Walleij]

On Tue, Jan 20, 2026 at 7:16 PM Conor Dooley <conor@kernel.org> wrote:

> From: Conor Dooley <conor.dooley@microchip.com>
>
> Hey Linus,
>
> Rebased as requested, with the dts patch that snuck in dropped.

Excellent, patches applied!

Thanks Conor!

Yours,
Linus Walleij