From: Sumit Gupta <sumitg@nvidia.com>
To: <treding@nvidia.com>, <jonathanh@nvidia.com>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <bbasu@nvidia.com>, <sumitg@nvidia.com>
Subject: [PATCH 3/3] arm64: dts: tegra264: Populate CPU and L2 cache nodes
Date: Wed, 21 Jan 2026 16:15:36 +0530 [thread overview]
Message-ID: <20260121104536.3214101-4-sumitg@nvidia.com> (raw)
In-Reply-To: <20260121104536.3214101-1-sumitg@nvidia.com>
Add the remaining 12 CPU nodes and all 14 L2 cache nodes for the
Tegra264 CPU Complex, which comprises up to 14 ARM Neoverse V3AE
CPUs. Each CPU has its own private 1MB L2 cache.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 321 +++++++++++++++++++++++
1 file changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index fa00e95f87a3..24cc2c51a272 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3786,6 +3786,7 @@ cpu0: cpu@0 {
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
+ next-level-cache = <&l2c0>;
};
cpu1: cpu@10000 {
@@ -3801,7 +3802,327 @@ cpu1: cpu@10000 {
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
+ next-level-cache = <&l2c1>;
};
+
+ cpu2: cpu@20000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x20000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c2>;
+ };
+
+ cpu3: cpu@30000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x30000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c3>;
+ };
+
+ cpu4: cpu@40000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x40000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c4>;
+ };
+
+ cpu5: cpu@50000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x50000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c5>;
+ };
+
+ cpu6: cpu@60000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x60000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c6>;
+ };
+
+ cpu7: cpu@70000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x70000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c7>;
+ };
+
+ cpu8: cpu@80000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x80000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c8>;
+ };
+
+ cpu9: cpu@90000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x90000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c9>;
+ };
+
+ cpu10: cpu@a0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xa0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c10>;
+ };
+
+ cpu11: cpu@b0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xb0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c11>;
+ };
+
+ cpu12: cpu@c0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xc0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c12>;
+ };
+
+ cpu13: cpu@d0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xd0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c13>;
+ };
+
+ l2c0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c2: l2-cache-2 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c3: l2-cache-3 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c4: l2-cache-4 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c5: l2-cache-5 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c6: l2-cache-6 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c7: l2-cache-7 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c8: l2-cache-8 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c9: l2-cache-9 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c10: l2-cache-10 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c11: l2-cache-11 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c12: l2-cache-12 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c13: l2-cache-13 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
};
bpmp: bpmp {
--
2.34.1
prev parent reply other threads:[~2026-01-21 10:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-21 10:45 [PATCH 0/3] arm64: dts: tegra: CPU and cache node updates Sumit Gupta
2026-01-21 10:45 ` [PATCH 1/3] arm64: dts: tegra234: Fix CPU compatible string to cortex-a78ae Sumit Gupta
2026-01-21 10:45 ` [PATCH 2/3] arm64: dts: tegra264: Fix CPU1 node unit-address Sumit Gupta
2026-01-21 10:45 ` Sumit Gupta [this message]
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