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From: Conor Dooley <conor@kernel.org>
To: Guodong Xu <guodong@riscstar.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Samuel Holland <samuel.holland@sifive.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Evan Green <evan@rivosinc.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] riscv: cpufeature: Clarify ISA spec version for canonical order
Date: Thu, 22 Jan 2026 18:56:42 +0000	[thread overview]
Message-ID: <20260122-arrive-undertook-413b9b9491fb@spud> (raw)
In-Reply-To: <20260116-supm-ext-id-v1-3-5fcf778ba4a6@riscstar.com>

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On Fri, Jan 16, 2026 at 10:10:33AM +0800, Guodong Xu wrote:
> Specify that chapter 27 refers to version 20191213 of the RISC-V ISA
> Unprivileged Architecture. The chapter numbering differs across
> specification versions - for example, in version 20250508, the ISA
> Extension Naming Conventions is chapter 36, not chapter 27.
> 
> Historical versions of the RISC-V specification can be found via Link [1].
> 
> Link: https://riscv.org/specifications/ratified/ [1]
> Fixes: 8135ade32c0db ("RISC-V: shunt isa_ext_arr to cpufeature.c")

I don't think that's the right fixes tag, if a fixes tag is even
appropriate. If a fixes tag is to be used, it should actually be
Fixes: 99e2266f2460 ("RISC-V: clarify ISA string ordering rules in cpu.c")

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 39680280f858..629984df1e7b 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -461,7 +461,8 @@ static const unsigned int riscv_supm_exts[] = {
>  
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
> - * chapter 27 of the unprivileged specification.
> + * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
> + * (Document Version 20191213).
>   *
>   * Ordinarily, for in-kernel data structures, this order is unimportant but
>   * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
> 
> -- 
> 2.43.0
> 

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      reply	other threads:[~2026-01-22 18:56 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-16  2:10 [PATCH 0/3] riscv: cpufeature: Add Supm extension id and validation Guodong Xu
2026-01-16  2:10 ` [PATCH 1/3] dt-bindings: riscv: Add Supm extension description Guodong Xu
2026-01-22 18:52   ` Conor Dooley
2026-01-22 23:29     ` Guodong Xu
2026-01-23 17:24       ` Conor Dooley
2026-01-16  2:10 ` [PATCH 2/3] riscv: cpufeature: Add ISA extension parsing for Supm Guodong Xu
2026-01-22 18:53   ` Conor Dooley
2026-01-16  2:10 ` [PATCH 3/3] riscv: cpufeature: Clarify ISA spec version for canonical order Guodong Xu
2026-01-22 18:56   ` Conor Dooley [this message]

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