* [PATCH v3 1/3] arm: dts: ti: omap: align node patterns with established convention
2026-01-22 17:52 [PATCH v3 0/3] dt-bindings: phy: Convert TI OMAP control and PIPE3 PHY to DT schema Charan Pedumuru
@ 2026-01-22 17:52 ` Charan Pedumuru
2026-01-22 17:52 ` [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema Charan Pedumuru
2026-01-22 17:52 ` [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: " Charan Pedumuru
2 siblings, 0 replies; 7+ messages in thread
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
Update OMAP DTS node patterns to match established conventions.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 4 ++--
arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 4 ++--
arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi
index c9282f57ffa5..ed206eb84d02 100644
--- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi
@@ -328,7 +328,7 @@ ocp2scp@0 {
ranges = <0 0 0x8000>;
reg = <0x0 0x20>;
- pcie1_phy: pciephy@4000 {
+ pcie1_phy: pcie-phy@4000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4000 0x80>, /* phy_rx */
<0x4400 0x64>; /* phy_tx */
@@ -348,7 +348,7 @@ pcie1_phy: pciephy@4000 {
#phy-cells = <0>;
};
- pcie2_phy: pciephy@5000 {
+ pcie2_phy: pcie-phy@5000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x5000 0x80>, /* phy_rx */
<0x5400 0x64>; /* phy_tx */
diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
index 4ee53dfb71b4..d8b16cbe6c35 100644
--- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
@@ -72,13 +72,13 @@ scm_conf: scm_conf@0 {
#size-cells = <1>;
};
- omap_control_usb2phy: control-phy@300 {
+ omap_control_usb2phy: phy@300 {
compatible = "ti,control-phy-usb2";
reg = <0x300 0x4>;
reg-names = "power";
};
- omap_control_usbotg: control-phy@33c {
+ omap_control_usbotg: phy@33c {
compatible = "ti,control-phy-otghs";
reg = <0x33c 0x4>;
reg-names = "otghs_control";
diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi
index 9f6100c7c34d..5c94db589dd1 100644
--- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi
@@ -472,7 +472,7 @@ usb2_phy: usb2phy@4000 {
#phy-cells = <0>;
};
- usb3_phy: usb3phy@4400 {
+ usb3_phy: usb3-phy@4400 {
compatible = "ti,omap-usb3";
reg = <0x4400 0x80>,
<0x4800 0x64>,
--
2.52.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema
2026-01-22 17:52 [PATCH v3 0/3] dt-bindings: phy: Convert TI OMAP control and PIPE3 PHY to DT schema Charan Pedumuru
2026-01-22 17:52 ` [PATCH v3 1/3] arm: dts: ti: omap: align node patterns with established convention Charan Pedumuru
@ 2026-01-22 17:52 ` Charan Pedumuru
2026-01-22 23:33 ` Rob Herring
2026-01-22 17:52 ` [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: " Charan Pedumuru
2 siblings, 1 reply; 7+ messages in thread
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
Convert TI PIPE3 PHY binding to DT schema.
Changes during conversion:
- Define a new pattern 'pcie-phy' to match nodes defined in DT.
- Drop obsolete "id" property from the schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
new file mode 100644
index 000000000000..605f12f0f79a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI PIPE3 PHY Module
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+description:
+ The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
+ transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
+ It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
+ interface standard, which defines a common physical layer for
+ high-speed serial interfaces.
+
+properties:
+ $nodename:
+ pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ti,omap-usb3
+ - ti,phy-pipe3-pcie
+ - ti,phy-pipe3-sata
+ - ti,phy-usb3
+
+ reg:
+ minItems: 2
+ maxItems: 3
+
+ reg-names:
+ minItems: 2
+ items:
+ - const: phy_rx
+ - const: phy_tx
+ - const: pll_ctrl
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 2
+ maxItems: 7
+
+ clock-names:
+ minItems: 2
+ maxItems: 7
+ items:
+ enum: [wkupclk, sysclk, refclk, dpll_ref,
+ dpll_ref_m2, phy-div, div-clk]
+
+ syscon-phy-power:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset controlling PHY power
+
+ syscon-pllreset:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset of CTRL_CORE_SMA_SW_0
+
+ syscon-pcs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset for PCS delay programming
+
+ ctrl-module:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of control module for PHY power on.
+ deprecated: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,phy-pipe3-sata
+ then:
+ properties:
+ syscon-pllreset: true
+ else:
+ properties:
+ syscon-pllreset: false
+
+required:
+ - reg
+ - compatible
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* TI PIPE3 USB3 PHY */
+ usb3-phy@4a084400 {
+ compatible = "ti,phy-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ #phy-cells = <0>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&sys_clkin>,
+ <&usb_otg_ss_refclk960m>;
+ clock-names = "wkupclk", "sysclk", "refclk";
+ ctrl-module = <&omap_control_usb>;
+ };
+
+ - |
+ /* TI PIPE3 SATA PHY */
+ phy@4a096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
+ #phy-cells = <0>;
+ };
+...
--
2.52.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema
2026-01-22 17:52 ` [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema Charan Pedumuru
@ 2026-01-22 23:33 ` Rob Herring
2026-01-23 13:12 ` Charan Pedumuru
0 siblings, 1 reply; 7+ messages in thread
From: Rob Herring @ 2026-01-22 23:33 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Vinod Koul, Neil Armstrong, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, Aaro Koskinen, Andreas Kemnade,
Kevin Hilman, Roger Quadros, Tony Lindgren, Roger Quadros,
linux-phy, devicetree, linux-kernel, linux-omap
On Thu, Jan 22, 2026 at 05:52:58PM +0000, Charan Pedumuru wrote:
> Convert TI PIPE3 PHY binding to DT schema.
> Changes during conversion:
> - Define a new pattern 'pcie-phy' to match nodes defined in DT.
> - Drop obsolete "id" property from the schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++++++
> 1 file changed, 135 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> new file mode 100644
> index 000000000000..605f12f0f79a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI PIPE3 PHY Module
> +
> +maintainers:
> + - Roger Quadros <rogerq@ti.com>
> +
> +description:
> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
> + interface standard, which defines a common physical layer for
> + high-speed serial interfaces.
> +
> +properties:
> + $nodename:
> + pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
> +
> + compatible:
> + enum:
> + - ti,omap-usb3
> + - ti,phy-pipe3-pcie
> + - ti,phy-pipe3-sata
> + - ti,phy-usb3
> +
> + reg:
> + minItems: 2
> + maxItems: 3
> +
> + reg-names:
> + minItems: 2
> + items:
> + - const: phy_rx
> + - const: phy_tx
> + - const: pll_ctrl
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + minItems: 2
> + maxItems: 7
> +
> + clock-names:
> + minItems: 2
> + maxItems: 7
> + items:
> + enum: [wkupclk, sysclk, refclk, dpll_ref,
> + dpll_ref_m2, phy-div, div-clk]
> +
> + syscon-phy-power:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: Phandle to the system control module
> + - description: Register offset controlling PHY power
This allows N entries of 2 cells each. You need either:
items:
- items:
- description: ...
- description: ...
(the hyphen is important!)
Or:
maxItems: 1
items:
items:
- description: ...
- description: ...
> +
> + syscon-pllreset:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: Phandle to the system control module
> + - description: Register offset of CTRL_CORE_SMA_SW_0
> +
> + syscon-pcs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: Phandle to the system control module
> + - description: Register offset for PCS delay programming
> +
> + ctrl-module:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of control module for PHY power on.
> + deprecated: true
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: ti,phy-pipe3-sata
> + then:
> + properties:
> + syscon-pllreset: true
> + else:
> + properties:
> + syscon-pllreset: false
> +
> +required:
> + - reg
> + - compatible
> + - reg-names
> + - "#phy-cells"
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + /* TI PIPE3 USB3 PHY */
> + usb3-phy@4a084400 {
> + compatible = "ti,phy-usb3";
> + reg = <0x4a084400 0x80>,
> + <0x4a084800 0x64>,
> + <0x4a084c00 0x40>;
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + #phy-cells = <0>;
> + clocks = <&usb_phy_cm_clk32k>,
> + <&sys_clkin>,
> + <&usb_otg_ss_refclk960m>;
> + clock-names = "wkupclk", "sysclk", "refclk";
> + ctrl-module = <&omap_control_usb>;
> + };
> +
> + - |
> + /* TI PIPE3 SATA PHY */
> + phy@4a096000 {
> + compatible = "ti,phy-pipe3-sata";
> + reg = <0x4A096000 0x80>, /* phy_rx */
> + <0x4A096400 0x64>, /* phy_tx */
> + <0x4A096800 0x40>; /* pll_ctrl */
Use lowercase hex.
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
> + clock-names = "sysclk", "refclk";
> + syscon-pllreset = <&scm_conf 0x3fc>;
> + #phy-cells = <0>;
> + };
> +...
>
> --
> 2.52.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema
2026-01-22 23:33 ` Rob Herring
@ 2026-01-23 13:12 ` Charan Pedumuru
0 siblings, 0 replies; 7+ messages in thread
From: Charan Pedumuru @ 2026-01-23 13:12 UTC (permalink / raw)
To: Rob Herring
Cc: Vinod Koul, Neil Armstrong, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, Aaro Koskinen, Andreas Kemnade,
Kevin Hilman, Roger Quadros, Tony Lindgren, Roger Quadros,
linux-phy, devicetree, linux-kernel, linux-omap
On 23-01-2026 05:03, Rob Herring wrote:
> On Thu, Jan 22, 2026 at 05:52:58PM +0000, Charan Pedumuru wrote:
>> Convert TI PIPE3 PHY binding to DT schema.
>> Changes during conversion:
>> - Define a new pattern 'pcie-phy' to match nodes defined in DT.
>> - Drop obsolete "id" property from the schema.
>>
>> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
>> ---
>> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++++++
>> 1 file changed, 135 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
>> new file mode 100644
>> index 000000000000..605f12f0f79a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
>> @@ -0,0 +1,135 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: TI PIPE3 PHY Module
>> +
>> +maintainers:
>> + - Roger Quadros <rogerq@ti.com>
>> +
>> +description:
>> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
>> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
>> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
>> + interface standard, which defines a common physical layer for
>> + high-speed serial interfaces.
>> +
>> +properties:
>> + $nodename:
>> + pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
>> +
>> + compatible:
>> + enum:
>> + - ti,omap-usb3
>> + - ti,phy-pipe3-pcie
>> + - ti,phy-pipe3-sata
>> + - ti,phy-usb3
>> +
>> + reg:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + reg-names:
>> + minItems: 2
>> + items:
>> + - const: phy_rx
>> + - const: phy_tx
>> + - const: pll_ctrl
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 7
>> + items:
>> + enum: [wkupclk, sysclk, refclk, dpll_ref,
>> + dpll_ref_m2, phy-div, div-clk]
>> +
>> + syscon-phy-power:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + items:
>> + - description: Phandle to the system control module
>> + - description: Register offset controlling PHY power
>
> This allows N entries of 2 cells each. You need either:
>
> items:
> - items:
> - description: ...
> - description: ...
>
> (the hyphen is important!)
>
> Or:
>
> maxItems: 1
> items:
> items:
> - description: ...
> - description: ...
Okay, I will use the above format in the next revision.
>
>> +
>> + syscon-pllreset:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + items:
>> + - description: Phandle to the system control module
>> + - description: Register offset of CTRL_CORE_SMA_SW_0
>> +
>> + syscon-pcs:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + items:
>> + - description: Phandle to the system control module
>> + - description: Register offset for PCS delay programming
>> +
>> + ctrl-module:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description:
>> + Phandle of control module for PHY power on.
>> + deprecated: true
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: ti,phy-pipe3-sata
>> + then:
>> + properties:
>> + syscon-pllreset: true
>> + else:
>> + properties:
>> + syscon-pllreset: false
>> +
>> +required:
>> + - reg
>> + - compatible
>> + - reg-names
>> + - "#phy-cells"
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + /* TI PIPE3 USB3 PHY */
>> + usb3-phy@4a084400 {
>> + compatible = "ti,phy-usb3";
>> + reg = <0x4a084400 0x80>,
>> + <0x4a084800 0x64>,
>> + <0x4a084c00 0x40>;
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + #phy-cells = <0>;
>> + clocks = <&usb_phy_cm_clk32k>,
>> + <&sys_clkin>,
>> + <&usb_otg_ss_refclk960m>;
>> + clock-names = "wkupclk", "sysclk", "refclk";
>> + ctrl-module = <&omap_control_usb>;
>> + };
>> +
>> + - |
>> + /* TI PIPE3 SATA PHY */
>> + phy@4a096000 {
>> + compatible = "ti,phy-pipe3-sata";
>> + reg = <0x4A096000 0x80>, /* phy_rx */
>> + <0x4A096400 0x64>, /* phy_tx */
>> + <0x4A096800 0x40>; /* pll_ctrl */
>
> Use lowercase hex.
Sure.
>
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
>> + clock-names = "sysclk", "refclk";
>> + syscon-pllreset = <&scm_conf 0x3fc>;
>> + #phy-cells = <0>;
>> + };
>> +...
>>
>> --
>> 2.52.0
>>
--
Best Regards,
Charan.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
2026-01-22 17:52 [PATCH v3 0/3] dt-bindings: phy: Convert TI OMAP control and PIPE3 PHY to DT schema Charan Pedumuru
2026-01-22 17:52 ` [PATCH v3 1/3] arm: dts: ti: omap: align node patterns with established convention Charan Pedumuru
2026-01-22 17:52 ` [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema Charan Pedumuru
@ 2026-01-22 17:52 ` Charan Pedumuru
2026-01-22 23:34 ` Rob Herring (Arm)
2 siblings, 1 reply; 7+ messages in thread
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
Convert TI OMAP Control PHY binding to DT schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../bindings/phy/ti,control-phy-otghs.yaml | 99 ++++++++++++++++++++++
Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ---------------------
2 files changed, 99 insertions(+), 98 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
new file mode 100644
index 000000000000..4ecb1611ee65
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI OMAP Control PHY Module
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+description:
+ The TI OMAP Control PHY module is a hardware block within the system
+ control module (SCM) of Texas Instruments OMAP SoCs. It provides
+ centralized control over power, configuration, and auxiliary features
+ for multiple on-chip PHYs. This module is essential for proper PHY
+ operation in power-constrained embedded systems.
+
+properties:
+ $nodename:
+ pattern: "^phy@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ti,control-phy-otghs
+ - ti,control-phy-pcie
+ - ti,control-phy-pipe3
+ - ti,control-phy-usb2
+ - ti,control-phy-usb2-am437
+ - ti,control-phy-usb2-dra7
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ enum: [otghs_control, power, pcie_pcs, control_sma]
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-otghs
+ then:
+ properties:
+ reg-names:
+ const: otghs_control
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-pcie
+ then:
+ properties:
+ reg:
+ minItems: 3
+
+ reg-names:
+ items:
+ - const: power
+ - const: pcie_pcs
+ - const: control_sma
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-usb2
+ - ti,control-phy-usb2-dra7
+ - ti,control-phy-usb2-am437
+ - ti,control-phy-pipe3
+ then:
+ properties:
+ reg-names:
+ const: power
+
+required:
+ - reg
+ - compatible
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ phy@4a00233c {
+ compatible = "ti,control-phy-otghs";
+ reg = <0x4a00233c 0x4>;
+ reg-names = "otghs_control";
+ };
+...
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
deleted file mode 100644
index 7c7936b89f2c..000000000000
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
-
-OMAP CONTROL PHY
-
-Required properties:
- - compatible: Should be one of
- "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
- "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
- set PCS delay value.
- e.g. PCIE PHY in DRA7x
- "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
- DRA7 platform.
- "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : register ranges as listed in the reg-names property
- - reg-names: "otghs_control" for control-phy-otghs
- "power", "pcie_pcs" and "control_sma" for control-phy-pcie
- "power" for all other types
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = "ti,control-phy-otghs";
- reg = <0x4a00233c 0x4>;
- reg-names = "otghs_control";
-};
-
-TI PIPE3 PHY
-
-Required properties:
- - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
- "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
- - reg : Address and length of the register set for the device.
- - reg-names: The names of the register addresses corresponding to the registers
- filled in "reg".
- - #phy-cells: determine the number of cells that should be given in the
- phandle while referencing this phy.
- - clocks: a list of phandles and clock-specifier pairs, one for each entry in
- clock-names.
- - clock-names: should include:
- * "wkupclk" - wakeup clock.
- * "sysclk" - system clock.
- * "refclk" - reference clock.
- * "dpll_ref" - external dpll ref clk
- * "dpll_ref_m2" - external dpll ref clk
- * "phy-div" - divider for apll
- * "div-clk" - apll clock
-
-Optional properties:
- - id: If there are multiple instance of the same type, in order to
- differentiate between each instance "id" can be used (e.g., multi-lane PCIe
- PHY). If "id" is not provided, it is set to default value of '1'.
- - syscon-pllreset: Handle to system control region that contains the
- CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
- register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
- - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
- register offset to write the PCS delay value.
-
-Deprecated properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
-
-Recommended properties:
- - syscon-phy-power : phandle/offset pair. Phandle to the system control
- module and the register offset to power on/off the PHY.
-
-This is usually a subnode of ocp2scp to which it is connected.
-
-usb3phy@4a084400 {
- compatible = "ti,phy-usb3";
- reg = <0x4a084400 0x80>,
- <0x4a084800 0x64>,
- <0x4a084c00 0x40>;
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_usb>;
- #phy-cells = <0>;
- clocks = <&usb_phy_cm_clk32k>,
- <&sys_clkin>,
- <&usb_otg_ss_refclk960m>;
- clock-names = "wkupclk",
- "sysclk",
- "refclk";
-};
-
-sata_phy: phy@4a096000 {
- compatible = "ti,phy-pipe3-sata";
- reg = <0x4A096000 0x80>, /* phy_rx */
- <0x4A096400 0x64>, /* phy_tx */
- <0x4A096800 0x40>; /* pll_ctrl */
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_sata>;
- clocks = <&sys_clkin1>, <&sata_ref_clk>;
- clock-names = "sysclk", "refclk";
- syscon-pllreset = <&scm_conf 0x3fc>;
- #phy-cells = <0>;
-};
--
2.52.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
2026-01-22 17:52 ` [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: " Charan Pedumuru
@ 2026-01-22 23:34 ` Rob Herring (Arm)
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring (Arm) @ 2026-01-22 23:34 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Kishon Vijay Abraham I, linux-kernel, Kevin Hilman,
Andreas Kemnade, Aaro Koskinen, Roger Quadros, Tony Lindgren,
Krzysztof Kozlowski, linux-phy, devicetree, Conor Dooley,
linux-omap, Vinod Koul, Neil Armstrong, Roger Quadros
On Thu, 22 Jan 2026 17:52:59 +0000, Charan Pedumuru wrote:
> Convert TI OMAP Control PHY binding to DT schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../bindings/phy/ti,control-phy-otghs.yaml | 99 ++++++++++++++++++++++
> Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ---------------------
> 2 files changed, 99 insertions(+), 98 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 7+ messages in thread