[PATCH 0/3] riscv: cpufeature: Add Supm extension id and validation

[PATCH 0/3] riscv: cpufeature: Add Supm extension id and validation

[Guodong Xu]

Supm as an extension indicates pointer-masking support for user mode
(U-mode). It relies on Ssnpm or Smnpm for the underlying hardware
implementation.

As a ratified feature, define a dedicated RISCV_ISA_EXT_ id for Supm.
However, since Supm is targeting U-mode, it should not be added into
devicetrees that describe hardware running privileged system softwares.

Supm is implied by Ssnpm (S-mode) or Smnpm (M-mode). Add parsing logic
and validation to ensure this dependency.

When CONFIG_RISCV_ISA_SUPM is disabled, Supm validation will fail
regardless of whether Ssnpm or Smnpm exist. This patchset doesn't change
this behavior.

Prior discussions about how Supm should be handled can be found in Links
[1] and [2].

Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@spud/#r [1]
Link: https://lore.kernel.org/all/4ebbe14b-2579-4ba6-808d-d50c24641d04@sifive.com/#r [2]

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Guodong Xu (3):
      dt-bindings: riscv: Add Supm extension description
      riscv: cpufeature: Add ISA extension parsing for Supm
      riscv: cpufeature: Clarify ISA spec version for canonical order

 .../devicetree/bindings/riscv/extensions.yaml      | 17 ++++++++++
 arch/riscv/include/asm/hwcap.h                     |  3 +-
 arch/riscv/kernel/cpufeature.c                     | 38 ++++++++++++++++++++--
 3 files changed, 53 insertions(+), 5 deletions(-)
---
base-commit: ef41e6187f77b52e4b17ab9637be8f878e1f7a5b
change-id: 20260116-supm-ext-id-826e8da4c4b5

Best regards,
-- 
Guodong Xu <guodong@riscstar.com>

[PATCH 1/3] dt-bindings: riscv: Add Supm extension description

[Guodong Xu]

Add description for the Supm extension. Supm indicates support for pointer
masking in user mode. Supm is mandatory for RVA23S64.

The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified
state") of riscv-j-extension.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 4ffd61926505..1922dff03787 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -262,6 +262,23 @@ properties:
             ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
             ("Updated to ratified state.")
 
+        - const: supm
+          description: |
+            The standard Supm extension for pointer masking support in user
+            mode (U-mode) as ratified at commit d70011dde6c2 ("Update to
+            ratified state") of riscv-j-extension.
+
+            Supm represents a combination of underlying hardware capability
+            (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode
+            software configuration that enables pointer masking for U-mode.
+
+            DO NOT include this property in device trees targeting privileged
+            system software (S-mode or M-mode).
+
+            This property is only appropriate in device trees provided to
+            U-mode software where the next-higher-privilege-mode supports
+            Smnpm or Ssnpm and enables it for U-mode.
+
         - const: svade
           description: |
             The standard Svade supervisor-level extension for SW-managed PTE A/D

-- 
2.43.0

[PATCH 2/3] riscv: cpufeature: Add ISA extension parsing for Supm

[Guodong Xu]

Supm has been ratified in the RISC-V Pointer Masking specification
(Version 1.0, 10/2024) and is mandated in RVA23 Profiles (Version 1.0,
2024-10-17) for RVA23U64. Supm indicates userspace pointer masking
support.

Remove the previous macro aliasing of Supm to Ssnpm/Smnpm in hwcap.h,
treating Supm as a distinct RISC-V ISA extension ID.

Add ISA parsing logic for Supm, and implement a validator to ensure
that Supm is only reported as available if Kconfig allows it and the
underlying Ssnpm (for supervisor mode) or Smnpm (for machine mode)
extension is present. Supm relies on Ssnpm or Smnpm to provide the
underlying hardware implementation.

With this change, "supm" will be reported (when available) in
/proc/cpuinfo as part of the "isa" and "hart isa" string.

Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@spud/#r [1]
Link: https://lore.kernel.org/all/4ebbe14b-2579-4ba6-808d-d50c24641d04@sifive.com/#r [2]
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/include/asm/hwcap.h |  3 +--
 arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++++++++++++++++++++--
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4369a2338541..7653e5cff9ae 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -110,6 +110,7 @@
 #define RISCV_ISA_EXT_ZALASR		101
 #define RISCV_ISA_EXT_ZILSD		102
 #define RISCV_ISA_EXT_ZCLSD		103
+#define RISCV_ISA_EXT_SUPM		104
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
@@ -118,10 +119,8 @@
 
 #ifdef CONFIG_RISCV_M_MODE
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SMAIA
-#define RISCV_ISA_EXT_SUPM		RISCV_ISA_EXT_SMNPM
 #else
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SSAIA
-#define RISCV_ISA_EXT_SUPM		RISCV_ISA_EXT_SSNPM
 #endif
 
 #endif /* _ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fa591aff9d33..39680280f858 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -296,6 +296,27 @@ static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
 	return 0;
 }
 
+static int riscv_ext_supm_validate(const struct riscv_isa_ext_data *data,
+				   const unsigned long *isa_bitmap)
+{
+	if (!IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
+		return -EINVAL;
+
+	/*
+	 * Supm requires Ssnpm for S-mode or Smnpm for M-mode to provide
+	 * pointer masking for the U-mode execution environment.
+	 */
+	if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
+		if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SMNPM))
+			return 0;
+	} else {
+		if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSNPM))
+			return 0;
+	}
+
+	return -EPROBE_DEFER;
+}
+
 static const unsigned int riscv_a_exts[] = {
 	RISCV_ISA_EXT_ZAAMO,
 	RISCV_ISA_EXT_ZALRSC,
@@ -429,6 +450,15 @@ static const unsigned int riscv_c_exts[] = {
 	RISCV_ISA_EXT_ZCD,
 };
 
+/*
+ * Smnpm and Ssnpm provide pointer masking for the next lower privilege mode
+ * (U-mode), thus enabling Supm. Both extensions imply the same subset.
+ */
+static const unsigned int riscv_supm_exts[] = {
+	RISCV_ISA_EXT_XLINUXENVCFG,
+	RISCV_ISA_EXT_SUPM
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -552,12 +582,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
-	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
+	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
-	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
+	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+	__RISCV_ISA_EXT_DATA_VALIDATE(supm, RISCV_ISA_EXT_SUPM, riscv_ext_supm_validate),
 	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
 	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),

-- 
2.43.0

[PATCH 3/3] riscv: cpufeature: Clarify ISA spec version for canonical order

[Guodong Xu]

Specify that chapter 27 refers to version 20191213 of the RISC-V ISA
Unprivileged Architecture. The chapter numbering differs across
specification versions - for example, in version 20250508, the ISA
Extension Naming Conventions is chapter 36, not chapter 27.

Historical versions of the RISC-V specification can be found via Link [1].

Link: https://riscv.org/specifications/ratified/ [1]
Fixes: 8135ade32c0db ("RISC-V: shunt isa_ext_arr to cpufeature.c")
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/kernel/cpufeature.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 39680280f858..629984df1e7b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -461,7 +461,8 @@ static const unsigned int riscv_supm_exts[] = {
 
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
- * chapter 27 of the unprivileged specification.
+ * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
+ * (Document Version 20191213).
  *
  * Ordinarily, for in-kernel data structures, this order is unimportant but
  * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.

-- 
2.43.0

Re: [PATCH 1/3] dt-bindings: riscv: Add Supm extension description

[Conor Dooley]

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On Fri, Jan 16, 2026 at 10:10:31AM +0800, Guodong Xu wrote:
> Add description for the Supm extension. Supm indicates support for pointer
> masking in user mode. Supm is mandatory for RVA23S64.
> 
> The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified
> state") of riscv-j-extension.
> 
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
>  Documentation/devicetree/bindings/riscv/extensions.yaml | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 4ffd61926505..1922dff03787 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -262,6 +262,23 @@ properties:
>              ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
>              ("Updated to ratified state.")
>  
> +        - const: supm
> +          description: |
> +            The standard Supm extension for pointer masking support in user
> +            mode (U-mode) as ratified at commit d70011dde6c2 ("Update to
> +            ratified state") of riscv-j-extension.
> +
> +            Supm represents a combination of underlying hardware capability
> +            (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode

Should we therefore make this require that Smnpm or Ssnpm are present?

> +            software configuration that enables pointer masking for U-mode.
> +
> +            DO NOT include this property in device trees targeting privileged
> +            system software (S-mode or M-mode).
> +
> +            This property is only appropriate in device trees provided to
> +            U-mode software where the next-higher-privilege-mode supports
> +            Smnpm or Ssnpm and enables it for U-mode.
> +
>          - const: svade
>            description: |
>              The standard Svade supervisor-level extension for SW-managed PTE A/D
> 
> -- 
> 2.43.0
> 

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Re: [PATCH 2/3] riscv: cpufeature: Add ISA extension parsing for Supm

[Conor Dooley]

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On Fri, Jan 16, 2026 at 10:10:32AM +0800, Guodong Xu wrote:
> Supm has been ratified in the RISC-V Pointer Masking specification
> (Version 1.0, 10/2024) and is mandated in RVA23 Profiles (Version 1.0,
> 2024-10-17) for RVA23U64. Supm indicates userspace pointer masking
> support.
> 
> Remove the previous macro aliasing of Supm to Ssnpm/Smnpm in hwcap.h,
> treating Supm as a distinct RISC-V ISA extension ID.
> 
> Add ISA parsing logic for Supm, and implement a validator to ensure
> that Supm is only reported as available if Kconfig allows it and the
> underlying Ssnpm (for supervisor mode) or Smnpm (for machine mode)
> extension is present. Supm relies on Ssnpm or Smnpm to provide the
> underlying hardware implementation.
> 
> With this change, "supm" will be reported (when available) in
> /proc/cpuinfo as part of the "isa" and "hart isa" string.
> 
> Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@spud/#r [1]
> Link: https://lore.kernel.org/all/4ebbe14b-2579-4ba6-808d-d50c24641d04@sifive.com/#r [2]
> Signed-off-by: Guodong Xu <guodong@riscstar.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


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Re: [PATCH 3/3] riscv: cpufeature: Clarify ISA spec version for canonical order

[Conor Dooley]

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On Fri, Jan 16, 2026 at 10:10:33AM +0800, Guodong Xu wrote:
> Specify that chapter 27 refers to version 20191213 of the RISC-V ISA
> Unprivileged Architecture. The chapter numbering differs across
> specification versions - for example, in version 20250508, the ISA
> Extension Naming Conventions is chapter 36, not chapter 27.
> 
> Historical versions of the RISC-V specification can be found via Link [1].
> 
> Link: https://riscv.org/specifications/ratified/ [1]
> Fixes: 8135ade32c0db ("RISC-V: shunt isa_ext_arr to cpufeature.c")

I don't think that's the right fixes tag, if a fixes tag is even
appropriate. If a fixes tag is to be used, it should actually be
Fixes: 99e2266f2460 ("RISC-V: clarify ISA string ordering rules in cpu.c")

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 39680280f858..629984df1e7b 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -461,7 +461,8 @@ static const unsigned int riscv_supm_exts[] = {
>  
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
> - * chapter 27 of the unprivileged specification.
> + * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
> + * (Document Version 20191213).
>   *
>   * Ordinarily, for in-kernel data structures, this order is unimportant but
>   * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
> 
> -- 
> 2.43.0
> 

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Re: [PATCH 1/3] dt-bindings: riscv: Add Supm extension description

[Guodong Xu]

On Fri, Jan 23, 2026 at 2:52 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Jan 16, 2026 at 10:10:31AM +0800, Guodong Xu wrote:
> > Add description for the Supm extension. Supm indicates support for pointer
> > masking in user mode. Supm is mandatory for RVA23S64.
> >
> > The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified
> > state") of riscv-j-extension.
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/extensions.yaml | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 4ffd61926505..1922dff03787 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -262,6 +262,23 @@ properties:
> >              ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
> >              ("Updated to ratified state.")
> >
> > +        - const: supm
> > +          description: |
> > +            The standard Supm extension for pointer masking support in user
> > +            mode (U-mode) as ratified at commit d70011dde6c2 ("Update to
> > +            ratified state") of riscv-j-extension.
> > +
> > +            Supm represents a combination of underlying hardware capability
> > +            (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode
>
> Should we therefore make this require that Smnpm or Ssnpm are present?

I'm not sure. Would U-mode DTBs typically omit the privileged extensions like
Smnpm/Ssnpm, making such a dependency impractical?

-Guodong

>
> > +            software configuration that enables pointer masking for U-mode.
> > +
> > +            DO NOT include this property in device trees targeting privileged
> > +            system software (S-mode or M-mode).
> > +
> > +            This property is only appropriate in device trees provided to
> > +            U-mode software where the next-higher-privilege-mode supports
> > +            Smnpm or Ssnpm and enables it for U-mode.
> > +
> >          - const: svade
> >            description: |
> >              The standard Svade supervisor-level extension for SW-managed PTE A/D
> >
> > --
> > 2.43.0
> >

Re: [PATCH 1/3] dt-bindings: riscv: Add Supm extension description

[Conor Dooley]

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On Fri, Jan 23, 2026 at 07:29:52AM +0800, Guodong Xu wrote:
> On Fri, Jan 23, 2026 at 2:52 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Fri, Jan 16, 2026 at 10:10:31AM +0800, Guodong Xu wrote:
> > > Add description for the Supm extension. Supm indicates support for pointer
> > > masking in user mode. Supm is mandatory for RVA23S64.
> > >
> > > The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified
> > > state") of riscv-j-extension.
> > >
> > > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > > ---
> > >  Documentation/devicetree/bindings/riscv/extensions.yaml | 17 +++++++++++++++++
> > >  1 file changed, 17 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > index 4ffd61926505..1922dff03787 100644
> > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > @@ -262,6 +262,23 @@ properties:
> > >              ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
> > >              ("Updated to ratified state.")
> > >
> > > +        - const: supm
> > > +          description: |
> > > +            The standard Supm extension for pointer masking support in user
> > > +            mode (U-mode) as ratified at commit d70011dde6c2 ("Update to
> > > +            ratified state") of riscv-j-extension.
> > > +
> > > +            Supm represents a combination of underlying hardware capability
> > > +            (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode
> >
> > Should we therefore make this require that Smnpm or Ssnpm are present?
> 
> I'm not sure. Would U-mode DTBs typically omit the privileged extensions like
> Smnpm/Ssnpm, making such a dependency impractical?

I don't actually know of any u-mode software that uses a devicetree, but
my guy feeling is that people won't trim out the lower-priv mode things
because they might want/need to know if those features are available on the
platform.

> > > +            software configuration that enables pointer masking for U-mode.
> > > +
> > > +            DO NOT include this property in device trees targeting privileged
> > > +            system software (S-mode or M-mode).
> > > +
> > > +            This property is only appropriate in device trees provided to
> > > +            U-mode software where the next-higher-privilege-mode supports
> > > +            Smnpm or Ssnpm and enables it for U-mode.
> > > +
> > >          - const: svade
> > >            description: |
> > >              The standard Svade supervisor-level extension for SW-managed PTE A/D
> > >
> > > --
> > > 2.43.0
> > >

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