* [PATCH v2 0/3] Add Tenstorrent Atlantis Clock/Reset Controller
@ 2026-01-22 22:36 Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon Anirudh Srinivasan
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Anirudh Srinivasan @ 2026-01-22 22:36 UTC (permalink / raw)
To: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Anirudh Srinivasan,
Philipp Zabel
Cc: linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
This series adds support for a multifunctional register block
(implemented as a syscon) in the Tenstorrent Atlantis SoC,
whose main functionality is to serve clocks and resets.
This block is instantiated multiple times in the SoC, with
each block covering clock/resets from a different subsystem. This series
adds a driver that covers clocks and resets from the RCPU subsystem,
which covers most low speed IO interfaces found in the chip. The reset
controller is implemented as an auxiliary device of the clock controller
and shares the same regmap as it.
The first commit adds bindings documenting the syscon block, along with
clock and reset indices. The second commit adds the reset controller
driver along with the auxdev definitions needed for it. The third commit
adds the clock controller driver, and the reset controller is created as
an auxdev of it.
Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
---
Changes in v2:
- Improve the documentation about the syscon block in bindings
- Implemented all clks using custom ops
- Removed custom lock/lock handling functions for regmap
- Addressed comments on header file ordering, newlines and typos
- Removed code for mux parent setting
- Squashed down multiple commits that added reset/auxdev separately
- Link to v1: https://lore.kernel.org/r/20260115-atlantis-clocks-v1-0-7356e671f28b@oss.tenstorrent.com
---
Anirudh Srinivasan (3):
dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon
reset: tenstorrent: Add reset controller for Atlantis
clk: tenstorrent: Add Atlantis clock controller driver
.../tenstorrent/tenstorrent,atlantis-syscon.yaml | 90 ++
MAINTAINERS | 5 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/tenstorrent/Kconfig | 14 +
drivers/clk/tenstorrent/Makefile | 3 +
drivers/clk/tenstorrent/atlantis-ccu.c | 939 +++++++++++++++++++++
drivers/reset/Kconfig | 11 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-tenstorrent-atlantis.c | 158 ++++
.../clock/tenstorrent,atlantis-syscon.h | 101 +++
include/soc/tenstorrent/atlantis-syscon.h | 53 ++
12 files changed, 1377 insertions(+)
---
base-commit: 9448598b22c50c8a5bb77a9103e2d49f134c9578
change-id: 20260112-atlantis-clocks-f090c190b86d
Best regards,
--
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon
2026-01-22 22:36 [PATCH v2 0/3] Add Tenstorrent Atlantis Clock/Reset Controller Anirudh Srinivasan
@ 2026-01-22 22:36 ` Anirudh Srinivasan
2026-01-23 7:10 ` Krzysztof Kozlowski
2026-01-22 22:36 ` [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver Anirudh Srinivasan
2 siblings, 1 reply; 11+ messages in thread
From: Anirudh Srinivasan @ 2026-01-22 22:36 UTC (permalink / raw)
To: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Anirudh Srinivasan,
Philipp Zabel
Cc: linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
Document bindings for Tenstorrent Atlantis syscon that manages clocks
and resets. This syscon block is instantiated 4 times in the SoC.
This commit documents the clocks from the RCPU syscon block.
Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
---
.../tenstorrent/tenstorrent,atlantis-syscon.yaml | 90 ++++++++++++++++++
MAINTAINERS | 2 +
.../clock/tenstorrent,atlantis-syscon.h | 101 +++++++++++++++++++++
3 files changed, 193 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
new file mode 100644
index 000000000000..49fbe2423be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tenstorrent Atlantis SoC Syscon
+
+maintainers:
+ - Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
+
+description:
+ Multifunctional register block found in Tenstorrent Atlantis SoC whose main function
+ is to control clocks and resets. This Block is instantiated multiple times in the SoC,
+ each block controls clock and resets for a different subsystem.
+
+ RCPU syscon serves low speed IO interfaces on chip
+ PCIe syscon serves all PCIe related functions
+ HSIO syscon serves high speed IO interfaces (Ethernet, USB)
+ MM syscon serves GPU, display and video processing functions
+
+properties:
+ compatible:
+ enum:
+ - tenstorrent,atlantis-syscon-rcpu
+ - tenstorrent,atlantis-syscon-pcie
+ - tenstorrent,atlantis-syscon-mm
+ - tenstorrent,atlantis-syscon-hsio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description:
+ See <dt-bindings/clock/tenstorrent,atlantis-syscon.h> for valid indices.
+
+ "#reset-cells":
+ const: 1
+
+ tenstorrent,syscon-rcpu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle reference to RCPU syscon, needed by other 3 syscons (PCIe, MM, HSIO)
+ as the control registers for the PLLs that drive these subsystems are in RCPU
+ syscon's range
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+ - "#reset-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tenstorrent,atlantis-syscon-pcie
+ - tenstorrent,atlantis-syscon-mm
+ - tenstorrent,atlantis-syscon-hsio
+ then:
+ required:
+ - tenstorrent,syscon-rcpu
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon_rcpu: system-controller@a8000000 {
+ compatible = "tenstorrent,atlantis-syscon-rcpu";
+ reg = <0xa8000000 0x10000>;
+ clocks = <&osc_24m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ syscon_hsio: system-controller@e00c0000 {
+ compatible = "tenstorrent,atlantis-syscon-hsio";
+ reg = <0xe00c0000 0x500>;
+ clocks = <&osc_24m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ tenstorrent,syscon-rcpu = <&syscon_rcpu>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index dc731d37c8fe..19a98b1fa456 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22535,7 +22535,9 @@ L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/tenstorrent/linux.git
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
F: arch/riscv/boot/dts/tenstorrent/
+F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
RISC-V THEAD SoC SUPPORT
M: Drew Fustini <fustini@kernel.org>
diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
new file mode 100644
index 000000000000..053cef2b43c8
--- /dev/null
+++ b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Tenstorrent
+ */
+
+#ifndef _DT_BINDINGS_ATLANTIS_SYSCON_H
+#define _DT_BINDINGS_ATLANTIS_SYSCON_H
+
+/*
+ * RCPU Domain Clock IDs
+ */
+#define CLK_RCPU_PLL 0
+#define CLK_RCPU_ROOT 1
+#define CLK_RCPU_DIV2 2
+#define CLK_RCPU_DIV4 3
+#define CLK_RCPU_RTC 4
+#define CLK_SMNDMA0_ACLK 5
+#define CLK_SMNDMA1_ACLK 6
+#define CLK_WDT0_PCLK 7
+#define CLK_WDT1_PCLK 8
+#define CLK_TIMER_PCLK 9
+#define CLK_PVTC_PCLK 10
+#define CLK_PMU_PCLK 11
+#define CLK_MAILBOX_HCLK 12
+#define CLK_SEC_SPACC_HCLK 13
+#define CLK_SEC_OTP_HCLK 14
+#define CLK_TRNG_PCLK 15
+#define CLK_SEC_CRC_HCLK 16
+#define CLK_SMN_HCLK 17
+#define CLK_AHB0_HCLK 18
+#define CLK_SMN_PCLK 19
+#define CLK_SMN_CLK 20
+#define CLK_SCRATCHPAD_CLK 21
+#define CLK_RCPU_CORE_CLK 22
+#define CLK_RCPU_ROM_CLK 23
+#define CLK_OTP_LOAD_CLK 24
+#define CLK_NOC_PLL 25
+#define CLK_NOCC_CLK 26
+#define CLK_NOCC_DIV2 27
+#define CLK_NOCC_DIV4 28
+#define CLK_NOCC_RTC 29
+#define CLK_NOCC_CAN 30
+#define CLK_QSPI_SCLK 31
+#define CLK_QSPI_HCLK 32
+#define CLK_I2C0_PCLK 33
+#define CLK_I2C1_PCLK 34
+#define CLK_I2C2_PCLK 35
+#define CLK_I2C3_PCLK 36
+#define CLK_I2C4_PCLK 37
+#define CLK_UART0_PCLK 38
+#define CLK_UART1_PCLK 39
+#define CLK_UART2_PCLK 40
+#define CLK_UART3_PCLK 41
+#define CLK_UART4_PCLK 42
+#define CLK_SPI0_PCLK 43
+#define CLK_SPI1_PCLK 44
+#define CLK_SPI2_PCLK 45
+#define CLK_SPI3_PCLK 46
+#define CLK_GPIO_PCLK 47
+#define CLK_CAN0_HCLK 48
+#define CLK_CAN0_CLK 49
+#define CLK_CAN1_HCLK 50
+#define CLK_CAN1_CLK 51
+#define CLK_CAN0_TIMER_CLK 52
+#define CLK_CAN1_TIMER_CLK 53
+
+/* RCPU domain reset */
+#define RST_SMNDMA0 0
+#define RST_SMNDMA1 1
+#define RST_WDT0 2
+#define RST_WDT1 3
+#define RST_TMR 4
+#define RST_PVTC 5
+#define RST_PMU 6
+#define RST_MAILBOX 7
+#define RST_SPACC 8
+#define RST_OTP 9
+#define RST_TRNG 10
+#define RST_CRC 11
+#define RST_QSPI 12
+#define RST_I2C0 13
+#define RST_I2C1 14
+#define RST_I2C2 15
+#define RST_I2C3 16
+#define RST_I2C4 17
+#define RST_UART0 18
+#define RST_UART1 19
+#define RST_UART2 20
+#define RST_UART3 21
+#define RST_UART4 22
+#define RST_SPI0 23
+#define RST_SPI1 24
+#define RST_SPI2 25
+#define RST_SPI3 26
+#define RST_GPIO 27
+#define RST_CAN0 28
+#define RST_CAN1 29
+#define RST_I2S0 30
+#define RST_I2S1 31
+
+#endif /* _DT_BINDINGS_ATLANTIS_SYSCON_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis
2026-01-22 22:36 [PATCH v2 0/3] Add Tenstorrent Atlantis Clock/Reset Controller Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon Anirudh Srinivasan
@ 2026-01-22 22:36 ` Anirudh Srinivasan
2026-01-23 13:00 ` Philipp Zabel
2026-01-22 22:36 ` [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver Anirudh Srinivasan
2 siblings, 1 reply; 11+ messages in thread
From: Anirudh Srinivasan @ 2026-01-22 22:36 UTC (permalink / raw)
To: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Anirudh Srinivasan,
Philipp Zabel
Cc: linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
Adds Atlantis Reset Controller and auxiliary device definitions for
reset to share same regmap interface as clock controller.
This version of the reset controller driver covers resets from the RCPU
syscon.
Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
---
MAINTAINERS | 2 +
drivers/reset/Kconfig | 11 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-tenstorrent-atlantis.c | 158 +++++++++++++++++++++++++++++
include/soc/tenstorrent/atlantis-syscon.h | 26 +++++
5 files changed, 198 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 19a98b1fa456..cf7c8e2153dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22537,7 +22537,9 @@ T: git https://github.com/tenstorrent/linux.git
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
F: arch/riscv/boot/dts/tenstorrent/
+F: drivers/reset/reset-tenstorrent-atlantis.c
F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
+F: include/soc/tenstorrent/
RISC-V THEAD SoC SUPPORT
M: Drew Fustini <fustini@kernel.org>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6e5d6deffa7d..cade77717492 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -324,6 +324,17 @@ config RESET_SUNXI
help
This enables the reset driver for Allwinner SoCs.
+config RESET_TENSTORRENT_ATLANTIS
+ tristate "Tenstorrent atlantis reset driver"
+ depends on ARCH_TENSTORRENT || COMPILE_TEST
+ select AUXILIARY_BUS
+ default ARCH_TENSTORRENT
+ help
+ This enables the driver for the reset controller
+ present in the Tenstorrent Atlantis SoC.
+ Enable this option to be able to use hardware
+ resets on Atalantis based systems.
+
config RESET_TH1520
tristate "T-HEAD TH1520 reset controller"
depends on ARCH_THEAD || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 9c3e484dfd81..a31959da0a88 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_TENSTORRENT_ATLANTIS) += reset-tenstorrent-atlantis.o
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
diff --git a/drivers/reset/reset-tenstorrent-atlantis.c b/drivers/reset/reset-tenstorrent-atlantis.c
new file mode 100644
index 000000000000..2e7f09409f79
--- /dev/null
+++ b/drivers/reset/reset-tenstorrent-atlantis.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2026 Tenstorrent
+ */
+
+#include <dt-bindings/clock/tenstorrent,atlantis-syscon.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <soc/tenstorrent/atlantis-syscon.h>
+
+struct atlantis_reset_data {
+ u8 bit;
+ u16 reg;
+ bool active_low;
+};
+
+struct atlantis_reset_controller_data {
+ const struct atlantis_reset_data *reset_data;
+ size_t count;
+};
+
+struct atlantis_reset_controller {
+ struct reset_controller_dev rcdev;
+ const struct atlantis_reset_controller_data *data;
+ struct regmap *regmap;
+};
+
+#define to_atlantis_reset_controller(_rcdev) \
+ container_of((_rcdev), struct atlantis_reset_controller, rcdev)
+
+#define RESET_DATA(_reg, _bit, _active_low) \
+ { \
+ .bit = _bit, .reg = _reg, .active_low = _active_low, \
+ }
+
+static const struct atlantis_reset_data atlantis_rcpu_resets[] = {
+ [RST_SMNDMA0] = RESET_DATA(RCPU_BLK_RST_REG, 0, true),
+ [RST_SMNDMA1] = RESET_DATA(RCPU_BLK_RST_REG, 1, true),
+ [RST_WDT0] = RESET_DATA(RCPU_BLK_RST_REG, 2, true),
+ [RST_WDT1] = RESET_DATA(RCPU_BLK_RST_REG, 3, true),
+ [RST_TMR] = RESET_DATA(RCPU_BLK_RST_REG, 4, true),
+ [RST_PVTC] = RESET_DATA(RCPU_BLK_RST_REG, 12, true),
+ [RST_PMU] = RESET_DATA(RCPU_BLK_RST_REG, 13, true),
+ [RST_MAILBOX] = RESET_DATA(RCPU_BLK_RST_REG, 14, true),
+ [RST_SPACC] = RESET_DATA(RCPU_BLK_RST_REG, 26, true),
+ [RST_OTP] = RESET_DATA(RCPU_BLK_RST_REG, 28, true),
+ [RST_TRNG] = RESET_DATA(RCPU_BLK_RST_REG, 29, true),
+ [RST_CRC] = RESET_DATA(RCPU_BLK_RST_REG, 30, true),
+ [RST_QSPI] = RESET_DATA(LSIO_BLK_RST_REG, 0, true),
+ [RST_I2C0] = RESET_DATA(LSIO_BLK_RST_REG, 1, true),
+ [RST_I2C1] = RESET_DATA(LSIO_BLK_RST_REG, 2, true),
+ [RST_I2C2] = RESET_DATA(LSIO_BLK_RST_REG, 3, true),
+ [RST_I2C3] = RESET_DATA(LSIO_BLK_RST_REG, 4, true),
+ [RST_I2C4] = RESET_DATA(LSIO_BLK_RST_REG, 5, true),
+ [RST_UART0] = RESET_DATA(LSIO_BLK_RST_REG, 6, true),
+ [RST_UART1] = RESET_DATA(LSIO_BLK_RST_REG, 7, true),
+ [RST_UART2] = RESET_DATA(LSIO_BLK_RST_REG, 8, true),
+ [RST_UART3] = RESET_DATA(LSIO_BLK_RST_REG, 9, true),
+ [RST_UART4] = RESET_DATA(LSIO_BLK_RST_REG, 10, true),
+ [RST_SPI0] = RESET_DATA(LSIO_BLK_RST_REG, 11, true),
+ [RST_SPI1] = RESET_DATA(LSIO_BLK_RST_REG, 12, true),
+ [RST_SPI2] = RESET_DATA(LSIO_BLK_RST_REG, 13, true),
+ [RST_SPI3] = RESET_DATA(LSIO_BLK_RST_REG, 14, true),
+ [RST_GPIO] = RESET_DATA(LSIO_BLK_RST_REG, 15, true),
+ [RST_CAN0] = RESET_DATA(LSIO_BLK_RST_REG, 17, true),
+ [RST_CAN1] = RESET_DATA(LSIO_BLK_RST_REG, 18, true),
+ [RST_I2S0] = RESET_DATA(LSIO_BLK_RST_REG, 19, true),
+ [RST_I2S1] = RESET_DATA(LSIO_BLK_RST_REG, 20, true),
+
+};
+
+static const struct atlantis_reset_controller_data atlantis_rcpu_reset_data = {
+ .reset_data = atlantis_rcpu_resets,
+ .count = ARRAY_SIZE(atlantis_rcpu_resets),
+};
+
+static int atlantis_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ unsigned int val;
+ struct atlantis_reset_controller *rst =
+ to_atlantis_reset_controller(rcdev);
+ const struct atlantis_reset_data *data = &rst->data->reset_data[id];
+ unsigned int mask = BIT(data->bit);
+ struct regmap *regmap = rst->regmap;
+
+ if (data->active_low ^ assert)
+ val = mask;
+ else
+ val = ~mask;
+
+ return regmap_update_bits(regmap, data->reg, mask, val);
+}
+
+static int atlantis_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return atlantis_reset_update(rcdev, id, true);
+}
+
+static int atlantis_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return atlantis_reset_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops atlantis_reset_control_ops = {
+ .assert = atlantis_reset_assert,
+ .deassert = atlantis_reset_deassert,
+};
+
+static int
+atlantis_reset_controller_register(struct device *dev,
+ struct atlantis_reset_controller *controller)
+{
+ struct reset_controller_dev *rcdev = &controller->rcdev;
+
+ rcdev->ops = &atlantis_reset_control_ops;
+ rcdev->owner = THIS_MODULE;
+ rcdev->of_node = dev->of_node;
+ rcdev->nr_resets = controller->data->count;
+
+ return devm_reset_controller_register(dev, &controller->rcdev);
+}
+static int atlantis_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct atlantis_ccu_adev *rdev = to_atlantis_ccu_adev(adev);
+ struct atlantis_reset_controller *controller;
+ struct device *dev = &adev->dev;
+
+ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
+ if (!controller)
+ return -ENOMEM;
+ controller->data =
+ (const struct atlantis_reset_controller_data *)id->driver_data;
+ controller->regmap = rdev->regmap;
+
+ return atlantis_reset_controller_register(dev, controller);
+}
+
+static const struct auxiliary_device_id atlantis_reset_ids[] = {
+ { .name = "atlantis_ccu.rcpu-reset",
+ .driver_data = (kernel_ulong_t)&atlantis_rcpu_reset_data },
+ {},
+};
+MODULE_DEVICE_TABLE(auxiliary, atlantis_reset_ids);
+
+static struct auxiliary_driver atlantis_reset_driver = {
+ .probe = atlantis_reset_probe,
+ .id_table = atlantis_reset_ids,
+};
+module_auxiliary_driver(atlantis_reset_driver);
+
+MODULE_AUTHOR("Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>");
+MODULE_DESCRIPTION("Atlantis reset controller driver");
+MODULE_LICENSE("GPL");
diff --git a/include/soc/tenstorrent/atlantis-syscon.h b/include/soc/tenstorrent/atlantis-syscon.h
new file mode 100644
index 000000000000..2c6387e5c21a
--- /dev/null
+++ b/include/soc/tenstorrent/atlantis-syscon.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Tenstorrent
+ */
+#ifndef __SOC_ATLANTIS_SYSCON_H__
+#define __SOC_ATLANTIS_SYSCON_H__
+
+#include <linux/bits.h>
+#include <linux/types.h>
+
+struct atlantis_ccu_adev {
+ struct auxiliary_device adev;
+ struct regmap *regmap;
+};
+
+#define to_atlantis_ccu_adev(_adev) \
+ container_of((_adev), struct atlantis_ccu_adev, adev)
+
+/* RCPU Reset Register Offsets */
+#define RCPU_BLK_RST_REG 0x001c
+#define LSIO_BLK_RST_REG 0x0020
+#define HSIO_BLK_RST_REG 0x000c
+#define PCIE_SUBS_RST_REG 0x0000
+#define MM_RSTN_REG 0x0014
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver
2026-01-22 22:36 [PATCH v2 0/3] Add Tenstorrent Atlantis Clock/Reset Controller Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis Anirudh Srinivasan
@ 2026-01-22 22:36 ` Anirudh Srinivasan
2026-01-23 7:03 ` kernel test robot
2026-01-23 11:41 ` kernel test robot
2 siblings, 2 replies; 11+ messages in thread
From: Anirudh Srinivasan @ 2026-01-22 22:36 UTC (permalink / raw)
To: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Anirudh Srinivasan,
Philipp Zabel
Cc: linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
Add driver for clock controller in Tenstorrent Atlantis SoC. This version
of the driver coves clocks from RCPU syscon.
5 types of clocks generated by this controller: PLLs (PLLs
with bypass functionality and an additional Gate clk at output), Shared
Gates (Multiple Gate clks that share an enable bit), standard Muxes,
Dividers and Gates. All clocks are implemented using custom clk ops and
use the regmap interface associated with the syscon. All clocks are derived
from a 24 Mhz oscillator.
The reset controller is also setup as an auxiliary device of the clock
controller.
Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
---
MAINTAINERS | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/tenstorrent/Kconfig | 14 +
drivers/clk/tenstorrent/Makefile | 3 +
drivers/clk/tenstorrent/atlantis-ccu.c | 939 ++++++++++++++++++++++++++++++
include/soc/tenstorrent/atlantis-syscon.h | 27 +
7 files changed, 986 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cf7c8e2153dc..31c3e5bcb32d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22537,6 +22537,7 @@ T: git https://github.com/tenstorrent/linux.git
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
F: arch/riscv/boot/dts/tenstorrent/
+F: drivers/clk/tenstorrent/
F: drivers/reset/reset-tenstorrent-atlantis.c
F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
F: include/soc/tenstorrent/
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3a1611008e48..643084887257 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -542,6 +542,7 @@ source "drivers/clk/starfive/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sunxi-ng/Kconfig"
source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/tenstorrent/Kconfig"
source "drivers/clk/thead/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/ti/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 61ec08404442..f88c116d315f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -156,6 +156,7 @@ obj-y += starfive/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-y += sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
+obj-y += tenstorrent/
obj-$(CONFIG_ARCH_THEAD) += thead/
obj-y += ti/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
diff --git a/drivers/clk/tenstorrent/Kconfig b/drivers/clk/tenstorrent/Kconfig
new file mode 100644
index 000000000000..6bcef9e4feb4
--- /dev/null
+++ b/drivers/clk/tenstorrent/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config TENSTORRENT_ATLANTIS_CCU
+ tristate "Support for Tenstorrent Atlantis Clock Controllers"
+ depends on ARCH_TENSTORRENT || COMPILE_TEST
+ default ARCH_TENSTORRENT
+ select REGMAP_MMIO
+ select AUXILIARY_BUS
+ select MFD_SYSCON
+ help
+ Say yes here to support the different clock
+ controllers found in the Tenstorrent Atlantis SoC.
+ This includes the clocks from the RCPU, HSIO, MMIO
+ and PCIE domain.
diff --git a/drivers/clk/tenstorrent/Makefile b/drivers/clk/tenstorrent/Makefile
new file mode 100644
index 000000000000..cc4fc01df75b
--- /dev/null
+++ b/drivers/clk/tenstorrent/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_TENSTORRENT_ATLANTIS_CCU) += atlantis-ccu.o
diff --git a/drivers/clk/tenstorrent/atlantis-ccu.c b/drivers/clk/tenstorrent/atlantis-ccu.c
new file mode 100644
index 000000000000..a4ad2fc3b621
--- /dev/null
+++ b/drivers/clk/tenstorrent/atlantis-ccu.c
@@ -0,0 +1,939 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 Tenstorrent
+ */
+
+#include <dt-bindings/clock/tenstorrent,atlantis-syscon.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <soc/tenstorrent/atlantis-syscon.h>
+
+struct atlantis_clk_common {
+ int clkid;
+ struct regmap *regmap;
+ struct clk_hw hw;
+};
+
+#define hw_to_atlantis_clk_common(_hw) \
+ container_of((_hw), struct atlantis_clk_common, hw)
+
+struct atlantis_clk_mux_config {
+ u8 shift;
+ u8 width;
+ u32 reg_offset;
+};
+
+struct atlantis_clk_mux {
+ struct atlantis_clk_common common;
+ struct atlantis_clk_mux_config config;
+};
+
+struct atlantis_clk_gate_config {
+ u32 reg_offset;
+ u32 enable;
+};
+
+struct atlantis_clk_gate {
+ struct atlantis_clk_common common;
+ struct atlantis_clk_gate_config config;
+};
+
+struct atlantis_clk_divider_config {
+ u8 shift;
+ u8 width;
+ u32 flags;
+ u32 reg_offset;
+};
+
+struct atlantis_clk_divider {
+ struct atlantis_clk_common common;
+ struct atlantis_clk_divider_config config;
+};
+
+struct atlantis_clk_pll_config {
+ u32 tbl_num;
+ u32 reg_offset;
+ u32 en_reg_offset;
+ u32 cg_reg_offset;
+ u32 cg_reg_enable;
+};
+
+/* Models a PLL with Bypass Functionality and Enable Bit + a Gate Clock at it's output */
+struct atlantis_clk_pll {
+ struct atlantis_clk_common common;
+ struct atlantis_clk_pll_config config;
+};
+
+struct atlantis_clk_gate_shared_config {
+ u32 reg_offset;
+ u32 enable;
+ unsigned int *share_count;
+ spinlock_t *refcount_lock;
+};
+
+struct atlantis_clk_gate_shared {
+ struct atlantis_clk_common common;
+ struct atlantis_clk_gate_shared_config config;
+};
+
+struct atlantis_clk_fixed_factor_config {
+ unsigned int mult;
+ unsigned int div;
+};
+
+struct atlantis_clk_fixed_factor {
+ struct atlantis_clk_fixed_factor_config config;
+ struct atlantis_clk_common common;
+};
+
+static inline struct atlantis_clk_mux *hw_to_atlantis_clk_mux(struct clk_hw *hw)
+{
+ struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
+
+ return container_of(common, struct atlantis_clk_mux, common);
+}
+
+static inline struct atlantis_clk_gate *
+hw_to_atlantis_clk_gate(struct clk_hw *hw)
+{
+ struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
+
+ return container_of(common, struct atlantis_clk_gate, common);
+}
+
+static inline struct atlantis_clk_divider *
+hw_to_atlantis_clk_divider(struct clk_hw *hw)
+{
+ struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
+
+ return container_of(common, struct atlantis_clk_divider, common);
+}
+
+static inline struct atlantis_clk_pll *hw_to_atlantis_pll(struct clk_hw *hw)
+{
+ struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
+
+ return container_of(common, struct atlantis_clk_pll, common);
+}
+
+static inline struct atlantis_clk_gate_shared *
+hw_to_atlantis_clk_gate_shared(struct clk_hw *hw)
+{
+ struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
+
+ return container_of(common, struct atlantis_clk_gate_shared, common);
+}
+
+static inline struct atlantis_clk_fixed_factor *
+hw_to_atlantis_clk_fixed_factor(struct clk_hw *hw)
+{
+ struct atlantis_clk_common *common = hw_to_atlantis_clk_common(hw);
+
+ return container_of(common, struct atlantis_clk_fixed_factor, common);
+}
+
+static u8 atlantis_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct atlantis_clk_mux *mux = hw_to_atlantis_clk_mux(hw);
+ u32 val;
+
+ regmap_read(mux->common.regmap, mux->config.reg_offset, &val);
+ val >>= mux->config.shift;
+ val &= (BIT(mux->config.width) - 1);
+
+ return val;
+}
+
+static int atlantis_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct atlantis_clk_mux *mux = hw_to_atlantis_clk_mux(hw);
+ u32 val = index;
+
+ return regmap_update_bits(mux->common.regmap, mux->config.reg_offset,
+ (BIT(mux->config.width) - 1)
+ << mux->config.shift,
+ val << mux->config.shift);
+}
+
+static int atlantis_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_mux_determine_rate_flags(hw, req, hw->init->flags);
+}
+
+const struct clk_ops atlantis_clk_mux_ops = {
+ .get_parent = atlantis_clk_mux_get_parent,
+ .set_parent = atlantis_clk_mux_set_parent,
+ .determine_rate = atlantis_clk_mux_determine_rate,
+};
+
+static void atlantis_clk_gate_endisable(struct clk_hw *hw, int enable)
+{
+ struct atlantis_clk_gate *gate = hw_to_atlantis_clk_gate(hw);
+ u32 val;
+
+ if (enable)
+ val = gate->config.enable;
+ else
+ val = ~(gate->config.enable);
+
+ regmap_update_bits(gate->common.regmap, gate->config.reg_offset,
+ gate->config.enable, val);
+}
+
+static int atlantis_clk_gate_enable(struct clk_hw *hw)
+{
+ atlantis_clk_gate_endisable(hw, 1);
+
+ return 0;
+}
+
+static void atlantis_clk_gate_disable(struct clk_hw *hw)
+{
+ atlantis_clk_gate_endisable(hw, 0);
+}
+
+static int atlantis_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct atlantis_clk_gate *gate = hw_to_atlantis_clk_gate(hw);
+ u32 val;
+
+ regmap_read(gate->common.regmap, gate->config.reg_offset, &val);
+
+ val &= gate->config.enable;
+
+ return val ? 1 : 0;
+}
+
+const struct clk_ops atlantis_clk_gate_ops = {
+ .enable = atlantis_clk_gate_enable,
+ .disable = atlantis_clk_gate_disable,
+ .is_enabled = atlantis_clk_gate_is_enabled,
+};
+
+static unsigned long atlantis_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct atlantis_clk_divider *divider = hw_to_atlantis_clk_divider(hw);
+ u32 val;
+
+ regmap_read(divider->common.regmap, divider->config.reg_offset, &val);
+
+ val >>= divider->config.shift;
+ val &= ((1 << (divider->config.width)) - 1);
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, val + 1);
+}
+
+const struct clk_ops atlantis_clk_divider_ops = {
+ .recalc_rate = atlantis_clk_divider_recalc_rate,
+};
+
+static unsigned long
+atlantis_clk_fixed_factor_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct atlantis_clk_fixed_factor *factor =
+ hw_to_atlantis_clk_fixed_factor(hw);
+ unsigned long long rate;
+
+ rate = (unsigned long long)parent_rate * factor->config.mult;
+ do_div(rate, factor->config.div);
+ return (unsigned long)rate;
+}
+
+const struct clk_ops atlantis_clk_fixed_factor_ops = {
+ .recalc_rate = atlantis_clk_fixed_factor_recalc_rate,
+};
+
+static int atlantis_clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
+ u32 val, en_val, cg_val;
+
+ regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
+ regmap_read(pll->common.regmap, pll->config.en_reg_offset, &en_val);
+ regmap_read(pll->common.regmap, pll->config.cg_reg_offset, &cg_val);
+
+ /* Check if PLL is powered on, locked and Gate clk is enabled */
+ return !!(en_val & PLL_CFG_EN_BIT) && !!(val & PLL_CFG_LOCK_BIT) &&
+ !!(cg_val && pll->config.cg_reg_enable);
+}
+
+static int atlantis_clk_pll_enable(struct clk_hw *hw)
+{
+ struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
+ u32 val, en_val, cg_val;
+ int ret;
+
+ regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
+ regmap_read(pll->common.regmap, pll->config.en_reg_offset, &en_val);
+ regmap_read(pll->common.regmap, pll->config.cg_reg_offset, &cg_val);
+
+ /* Check if PLL is already enabled, locked and Gate clk is enabled */
+ if ((en_val & PLL_CFG_EN_BIT) && (val & PLL_CFG_LOCK_BIT) &&
+ (cg_val && pll->config.cg_reg_enable) &&
+ !(val & PLL_CFG_BYPASS_BIT)) {
+ return 0;
+ }
+
+ /* Step 1: Set bypass mode first */
+ regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
+ PLL_CFG_BYPASS_BIT, PLL_CFG_BYPASS_BIT);
+
+ /* Step 2: Enable PLL (clear then set power bit) */
+ regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
+ PLL_CFG_EN_BIT, 0);
+
+ regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
+ PLL_CFG_EN_BIT, PLL_CFG_EN_BIT);
+
+ /* Step 3: Wait for PLL lock */
+ ret = regmap_read_poll_timeout(pll->common.regmap,
+ pll->config.reg_offset, val,
+ val & PLL_CFG_LOCK_BIT, 10,
+ PLL_BYPASS_WAIT_US);
+ if (ret) {
+ pr_err("PLL failed to lock within timeout\n");
+ return ret;
+ }
+
+ /* Step 4: Switch from bypass to PLL output */
+ regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
+ PLL_CFG_BYPASS_BIT, 0);
+
+ /* Enable Gate clk at PLL Output */
+ return regmap_update_bits(pll->common.regmap, pll->config.cg_reg_offset,
+ pll->config.cg_reg_enable,
+ pll->config.cg_reg_enable);
+}
+
+static void atlantis_clk_pll_disable(struct clk_hw *hw)
+{
+ struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
+
+ /* Step 1: Switch to bypass mode before disabling */
+ regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
+ PLL_CFG_BYPASS_BIT, PLL_CFG_BYPASS_BIT);
+ /* Step 2: Power down PLL */
+ regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
+ PLL_CFG_EN_BIT, 0);
+}
+
+static unsigned long atlantis_clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
+
+ u32 val, refdiv, fbdiv, postdiv1, postdiv2;
+ u64 fout;
+
+ regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
+
+ if (val & PLL_CFG_BYPASS_BIT)
+ return parent_rate;
+
+ refdiv = FIELD_GET(PLL_CFG_REFDIV_MASK, val);
+ fbdiv = FIELD_GET(PLL_CFG_FBDIV_MASK, val);
+ postdiv1 = FIELD_GET(PLL_CFG_POSTDIV1_MASK, val);
+ postdiv2 = FIELD_GET(PLL_CFG_POSTDIV2_MASK, val);
+
+ if (!refdiv)
+ refdiv = 1;
+ if (!postdiv1)
+ postdiv1 = 1;
+ if (!postdiv2)
+ postdiv2 = 1;
+ if (!fbdiv)
+ return 0;
+
+ fout = div64_u64((u64)parent_rate * fbdiv,
+ refdiv * postdiv1 * postdiv2);
+
+ return fout;
+}
+
+const struct clk_ops atlantis_clk_pll_ops = {
+ .enable = atlantis_clk_pll_enable,
+ .disable = atlantis_clk_pll_disable,
+ .recalc_rate = atlantis_clk_pll_recalc_rate,
+ .is_enabled = atlantis_clk_pll_is_enabled,
+};
+
+static int atlantis_clk_gate_shared_enable(struct clk_hw *hw)
+{
+ struct atlantis_clk_gate_shared *gate =
+ hw_to_atlantis_clk_gate_shared(hw);
+ bool need_enable;
+ u32 reg;
+
+ scoped_guard(spinlock_irqsave, gate->config.refcount_lock)
+ {
+ need_enable = (*gate->config.share_count)++ == 0;
+ if (need_enable) {
+ regmap_read(gate->common.regmap,
+ gate->config.reg_offset, ®);
+ reg |= gate->config.enable;
+ regmap_write(gate->common.regmap,
+ gate->config.reg_offset, reg);
+ }
+ }
+
+ if (need_enable) {
+ regmap_read(gate->common.regmap, gate->config.reg_offset, ®);
+
+ if (!(reg & gate->config.enable)) {
+ pr_warn("%s: gate enable %d failed to enable\n",
+ clk_hw_get_name(hw), gate->config.enable);
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+static void atlantis_clk_gate_shared_disable(struct clk_hw *hw)
+{
+ struct atlantis_clk_gate_shared *gate =
+ hw_to_atlantis_clk_gate_shared(hw);
+ u32 reg;
+
+ scoped_guard(spinlock_irqsave, gate->config.refcount_lock)
+ {
+ if (WARN_ON(*gate->config.share_count == 0))
+ return;
+ if (--(*gate->config.share_count) > 0)
+ return;
+
+ regmap_read(gate->common.regmap, gate->config.reg_offset, ®);
+ reg &= ~gate->config.enable;
+ regmap_write(gate->common.regmap, gate->config.reg_offset, reg);
+ }
+}
+
+static int atlantis_clk_gate_shared_is_enabled(struct clk_hw *hw)
+{
+ struct atlantis_clk_gate_shared *gate =
+ hw_to_atlantis_clk_gate_shared(hw);
+ u32 reg;
+
+ regmap_read(gate->common.regmap, gate->config.reg_offset, ®);
+
+ return !!(reg & gate->config.enable);
+}
+
+static void atlantis_clk_gate_shared_disable_unused(struct clk_hw *hw)
+{
+ struct atlantis_clk_gate_shared *gate =
+ hw_to_atlantis_clk_gate_shared(hw);
+
+ u32 reg;
+
+ scoped_guard(spinlock_irqsave, gate->config.refcount_lock)
+ {
+ if (*gate->config.share_count == 0) {
+ regmap_read(gate->common.regmap,
+ gate->config.reg_offset, ®);
+ reg &= ~gate->config.enable;
+ regmap_write(gate->common.regmap,
+ gate->config.reg_offset, reg);
+ }
+ }
+}
+
+const struct clk_ops atlantis_clk_gate_shared_ops = {
+ .enable = atlantis_clk_gate_shared_enable,
+ .disable = atlantis_clk_gate_shared_disable,
+ .disable_unused = atlantis_clk_gate_shared_disable_unused,
+ .is_enabled = atlantis_clk_gate_shared_is_enabled,
+};
+
+#define ATLANTIS_PLL_CONFIG(_reg_offset, _en_reg_offset, _cg_reg_offset, \
+ _cg_reg_enable) \
+ { \
+ .reg_offset = (_reg_offset), \
+ .en_reg_offset = (_en_reg_offset), \
+ .cg_reg_offset = (_cg_reg_offset), \
+ .cg_reg_enable = (_cg_reg_enable), \
+ }
+
+#define ATLANTIS_PLL_DEFINE(_clkid, _name, _parent, _reg_offset, \
+ _en_reg_offset, _cg_reg_offset, _cg_reg_enable, \
+ _flags) \
+ static struct atlantis_clk_pll _name = { \
+ .config = ATLANTIS_PLL_CONFIG(_reg_offset, _en_reg_offset, \
+ _cg_reg_offset, _cg_reg_enable), \
+ .common = { .clkid = _clkid, \
+ .hw.init = CLK_HW_INIT_PARENTS_DATA( \
+ #_name, _parent, &atlantis_clk_pll_ops, \
+ _flags) }, \
+ }
+#define ATLANTIS_MUX_CONFIG(_shift, _width, _reg_offset) \
+ { \
+ .shift = _shift, .width = _width, .reg_offset = _reg_offset \
+ }
+
+#define ATLANTIS_MUX_DEFINE(_clkid, _name, _parents, _reg_offset, _shift, \
+ _width, _flags) \
+ static struct atlantis_clk_mux _name = { \
+ .config = ATLANTIS_MUX_CONFIG(_shift, _width, _reg_offset), \
+ .common = { .clkid = _clkid, \
+ .hw.init = CLK_HW_INIT_PARENTS_DATA( \
+ #_name, _parents, &atlantis_clk_mux_ops, \
+ _flags) } \
+ }
+
+#define ATLANTIS_DIVIDER_CONFIG(_shift, _width, _flags, _reg_offset) \
+ { \
+ .shift = _shift, .width = _width, .flags = _flags, \
+ .reg_offset = _reg_offset \
+ }
+
+#define ATLANTIS_DIVIDER_DEFINE(_clkid, _name, _parent, _reg_offset, _shift, \
+ _width, _divflags, _flags) \
+ static struct atlantis_clk_divider _name = { \
+ .config = ATLANTIS_DIVIDER_CONFIG(_shift, _width, _divflags, \
+ _reg_offset), \
+ .common = { .clkid = _clkid, \
+ .hw.init = CLK_HW_INIT_HW( \
+ #_name, &_parent.common.hw, \
+ &atlantis_clk_divider_ops, _flags) } \
+ }
+#define ATLANTIS_GATE_CONFIG(_enable, _reg_offset) \
+ { \
+ .enable = _enable, .reg_offset = _reg_offset \
+ }
+
+#define ATLANTIS_GATE_DEFINE(_clkid, _name, _parent, _reg_offset, _enable, \
+ _flags) \
+ static struct atlantis_clk_gate _name = { \
+ .config = ATLANTIS_GATE_CONFIG(_enable, _reg_offset), \
+ .common = { .clkid = _clkid, \
+ .hw.init = CLK_HW_INIT_HW( \
+ #_name, &_parent.common.hw, \
+ &atlantis_clk_gate_ops, _flags) } \
+ }
+#define ATLANTIS_GATE_SHARED_CONFIG(_reg_offset, _enable, _share_count) \
+ { \
+ .reg_offset = _reg_offset, .enable = _enable, \
+ .share_count = _share_count, .refcount_lock = &refcount_lock \
+ }
+#define ATLANTIS_GATE_SHARED_DEFINE(_clkid, _name, _parent, _reg_offset, \
+ _enable, _share_count, _flags) \
+ static struct atlantis_clk_gate_shared _name = { \
+ .config = ATLANTIS_GATE_SHARED_CONFIG(_reg_offset, _enable, \
+ _share_count), \
+ .common = { .clkid = _clkid, \
+ .hw.init = CLK_HW_INIT_HW( \
+ #_name, &_parent.common.hw, \
+ &atlantis_clk_gate_shared_ops, _flags) } \
+ }
+#define ATLANTIS_CLK_FIXED_FACTOR_DEFINE(_clkid, _name, _parent, _mult, _div, \
+ _flags) \
+ static struct atlantis_clk_fixed_factor _name = { \
+ .config = { .mult = _mult, .div = _div }, \
+ .common = { .clkid = _clkid, \
+ .hw.init = CLK_HW_INIT_HW( \
+ #_name, &_parent.common.hw, \
+ &atlantis_clk_fixed_factor_ops, _flags) } \
+ }
+
+static DEFINE_SPINLOCK(refcount_lock); /* Lock for refcount value accesses */
+
+static const struct regmap_config atlantis_ccu_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xFFFC,
+ .cache_type = REGCACHE_NONE,
+};
+struct atlantis_ccu {
+ struct device *dev;
+
+ struct regmap *regmap;
+ void __iomem *base;
+
+ struct clk_hw_onecell_data *clk_data;
+};
+
+struct atlantis_ccu_data {
+ struct clk_hw **hws;
+ size_t num;
+ const char *reset_name;
+};
+
+static const struct clk_parent_data osc_24m_clk[] = {
+ { .index = 0 },
+};
+
+ATLANTIS_PLL_DEFINE(CLK_RCPU_PLL, rcpu_pll_clk, osc_24m_clk, RCPU_PLL_CFG_REG,
+ PLL_RCPU_EN_REG, BUS_CG_REG, BIT(7),
+ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_UNGATE |
+ CLK_IS_CRITICAL);
+
+static const struct clk_parent_data rcpu_root_parents[] = {
+ { .index = 0 },
+ { .hw = &rcpu_pll_clk.common.hw },
+};
+
+ATLANTIS_MUX_DEFINE(CLK_RCPU_ROOT, rcpu_root_mux, rcpu_root_parents,
+ RCPU_DIV_CFG_REG, 0, 1, CLK_SET_RATE_NO_REPARENT);
+
+ATLANTIS_DIVIDER_DEFINE(CLK_RCPU_DIV2, rcpu_div2_clk, rcpu_root_mux,
+ RCPU_DIV_CFG_REG, 2, 4, 0, 0);
+ATLANTIS_DIVIDER_DEFINE(CLK_RCPU_DIV4, rcpu_div4_clk, rcpu_root_mux,
+ RCPU_DIV_CFG_REG, 7, 4, 0, 0);
+ATLANTIS_DIVIDER_DEFINE(CLK_RCPU_RTC, rcpu_rtc_clk, rcpu_div4_clk,
+ RCPU_DIV_CFG_REG, 12, 6, 0, 0);
+
+ATLANTIS_GATE_DEFINE(CLK_SMNDMA0_ACLK, smndma0_aclk, rcpu_div2_clk,
+ RCPU_BLK_CG_REG, BIT(0), 0);
+ATLANTIS_GATE_DEFINE(CLK_SMNDMA1_ACLK, smndma1_aclk, rcpu_div2_clk,
+ RCPU_BLK_CG_REG, BIT(1), 0);
+ATLANTIS_GATE_DEFINE(CLK_WDT0_PCLK, wdt0_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
+ BIT(2), 0);
+ATLANTIS_GATE_DEFINE(CLK_WDT1_PCLK, wdt1_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
+ BIT(3), 0);
+ATLANTIS_GATE_DEFINE(CLK_TIMER_PCLK, timer_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
+ BIT(4), 0);
+ATLANTIS_GATE_DEFINE(CLK_PVTC_PCLK, pvtc_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
+ BIT(12), 0);
+ATLANTIS_GATE_DEFINE(CLK_PMU_PCLK, pmu_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
+ BIT(13), 0);
+ATLANTIS_GATE_DEFINE(CLK_MAILBOX_HCLK, mb_hclk, rcpu_div2_clk, RCPU_BLK_CG_REG,
+ BIT(14), 0);
+ATLANTIS_GATE_DEFINE(CLK_SEC_SPACC_HCLK, sec_spacc_hclk, rcpu_div2_clk,
+ RCPU_BLK_CG_REG, BIT(26), 0);
+ATLANTIS_GATE_DEFINE(CLK_SEC_OTP_HCLK, sec_otp_hclk, rcpu_div2_clk,
+ RCPU_BLK_CG_REG, BIT(28), 0);
+ATLANTIS_GATE_DEFINE(CLK_TRNG_PCLK, trng_pclk, rcpu_div4_clk, RCPU_BLK_CG_REG,
+ BIT(29), 0);
+ATLANTIS_GATE_DEFINE(CLK_SEC_CRC_HCLK, sec_crc_hclk, rcpu_div2_clk,
+ RCPU_BLK_CG_REG, BIT(30), 0);
+
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_SMN_HCLK, rcpu_smn_hclk, rcpu_div2_clk, 1,
+ 1, 0);
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_AHB0_HCLK, rcpu_ahb0_hclk, rcpu_div2_clk,
+ 1, 1, 0);
+
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_SMN_PCLK, rcpu_smn_pclk, rcpu_div4_clk, 1,
+ 1, 0);
+
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_SMN_CLK, rcpu_smn_clk, rcpu_root_mux, 1, 1,
+ 0);
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_SCRATCHPAD_CLK, rcpu_scratchpad_aclk,
+ rcpu_root_mux, 1, 1, 0);
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_RCPU_CORE_CLK, rcpu_core_clk,
+ rcpu_root_mux, 1, 1, 0);
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_RCPU_ROM_CLK, rcpu_rom_aclk, rcpu_root_mux,
+ 1, 1, 0);
+
+static struct atlantis_clk_fixed_factor
+ otp_load_clk = { .config = { .mult = 1, .div = 1 },
+ .common = {
+ .clkid = CLK_OTP_LOAD_CLK,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA(
+ "otp_load_clk", osc_24m_clk,
+ &atlantis_clk_fixed_factor_ops,
+ CLK_SET_RATE_NO_REPARENT),
+ } };
+
+ATLANTIS_PLL_DEFINE(CLK_NOC_PLL, nocc_pll_clk, osc_24m_clk,
+ RCPU_NOCC_PLL_CFG_REG, PLL_NOCC_EN_REG, BUS_CG_REG, BIT(0),
+ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_UNGATE |
+ CLK_IS_CRITICAL);
+
+static const struct clk_parent_data nocc_mux_parents[] = {
+ { .index = 0 },
+ { .hw = &nocc_pll_clk.common.hw },
+};
+
+ATLANTIS_MUX_DEFINE(CLK_NOCC_CLK, nocc_clk_mux, nocc_mux_parents,
+ RCPU_NOCC_CLK_CFG_REG, 0, 1, CLK_SET_RATE_NO_REPARENT);
+
+ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_DIV2, nocc_div2_clk, nocc_clk_mux,
+ RCPU_NOCC_CLK_CFG_REG, 1, 4, 0, 0);
+ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_DIV4, nocc_div4_clk, nocc_clk_mux,
+ RCPU_NOCC_CLK_CFG_REG, 5, 4, 0, 0);
+ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_RTC, nocc_rtc_clk, nocc_div4_clk,
+ RCPU_NOCC_CLK_CFG_REG, 9, 6, 0, 0);
+ATLANTIS_DIVIDER_DEFINE(CLK_NOCC_CAN, nocc_can_div, nocc_clk_mux,
+ RCPU_NOCC_CLK_CFG_REG, 15, 4, 0, 0);
+
+static unsigned int refcnt_qspi;
+ATLANTIS_GATE_SHARED_DEFINE(CLK_QSPI_SCLK, qspi_sclk, nocc_clk_mux,
+ LSIO_BLK_CG_REG, BIT(0), &refcnt_qspi, 0);
+ATLANTIS_GATE_SHARED_DEFINE(CLK_QSPI_HCLK, qspi_hclk, nocc_div2_clk,
+ LSIO_BLK_CG_REG, BIT(0), &refcnt_qspi, 0);
+ATLANTIS_GATE_DEFINE(CLK_I2C0_PCLK, i2c0_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(1), 0);
+ATLANTIS_GATE_DEFINE(CLK_I2C1_PCLK, i2c1_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(2), 0);
+ATLANTIS_GATE_DEFINE(CLK_I2C2_PCLK, i2c2_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(3), 0);
+ATLANTIS_GATE_DEFINE(CLK_I2C3_PCLK, i2c3_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(4), 0);
+ATLANTIS_GATE_DEFINE(CLK_I2C4_PCLK, i2c4_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(5), 0);
+
+ATLANTIS_GATE_DEFINE(CLK_UART0_PCLK, uart0_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(6), 0);
+ATLANTIS_GATE_DEFINE(CLK_UART1_PCLK, uart1_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(7), 0);
+ATLANTIS_GATE_DEFINE(CLK_UART2_PCLK, uart2_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(8), 0);
+ATLANTIS_GATE_DEFINE(CLK_UART3_PCLK, uart3_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(9), 0);
+ATLANTIS_GATE_DEFINE(CLK_UART4_PCLK, uart4_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(10), 0);
+ATLANTIS_GATE_DEFINE(CLK_SPI0_PCLK, spi0_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(11), 0);
+ATLANTIS_GATE_DEFINE(CLK_SPI1_PCLK, spi1_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(12), 0);
+ATLANTIS_GATE_DEFINE(CLK_SPI2_PCLK, spi2_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(13), 0);
+ATLANTIS_GATE_DEFINE(CLK_SPI3_PCLK, spi3_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(14), 0);
+ATLANTIS_GATE_DEFINE(CLK_GPIO_PCLK, gpio_pclk, nocc_div4_clk, LSIO_BLK_CG_REG,
+ BIT(15), 0);
+
+static unsigned int refcnt_can0;
+ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN0_HCLK, can0_hclk, nocc_div2_clk,
+ LSIO_BLK_CG_REG, BIT(17), &refcnt_can0, 0);
+ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN0_CLK, can0_clk, nocc_can_div,
+ LSIO_BLK_CG_REG, BIT(17), &refcnt_can0, 0);
+
+static unsigned int refcnt_can1;
+ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN1_HCLK, can1_hclk, nocc_div2_clk,
+ LSIO_BLK_CG_REG, BIT(18), &refcnt_can1, 0);
+ATLANTIS_GATE_SHARED_DEFINE(CLK_CAN1_CLK, can1_clk, nocc_can_div,
+ LSIO_BLK_CG_REG, BIT(18), &refcnt_can1, 0);
+
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_CAN0_TIMER_CLK, can0_timer_clk,
+ nocc_rtc_clk, 1, 1, 0);
+ATLANTIS_CLK_FIXED_FACTOR_DEFINE(CLK_CAN1_TIMER_CLK, can1_timer_clk,
+ nocc_rtc_clk, 1, 1, 0);
+
+static struct clk_hw *atlantis_rcpu_clks[] = {
+ [CLK_RCPU_PLL] = &rcpu_pll_clk.common.hw,
+ [CLK_RCPU_ROOT] = &rcpu_root_mux.common.hw,
+ [CLK_RCPU_DIV2] = &rcpu_div2_clk.common.hw,
+ [CLK_RCPU_DIV4] = &rcpu_div4_clk.common.hw,
+ [CLK_RCPU_RTC] = &rcpu_rtc_clk.common.hw,
+ [CLK_SMNDMA0_ACLK] = &smndma0_aclk.common.hw,
+ [CLK_SMNDMA1_ACLK] = &smndma1_aclk.common.hw,
+ [CLK_WDT0_PCLK] = &wdt0_pclk.common.hw,
+ [CLK_WDT1_PCLK] = &wdt1_pclk.common.hw,
+ [CLK_TIMER_PCLK] = &timer_pclk.common.hw,
+ [CLK_PVTC_PCLK] = &pvtc_pclk.common.hw,
+ [CLK_PMU_PCLK] = &pmu_pclk.common.hw,
+ [CLK_MAILBOX_HCLK] = &mb_hclk.common.hw,
+ [CLK_SEC_SPACC_HCLK] = &sec_spacc_hclk.common.hw,
+ [CLK_SEC_OTP_HCLK] = &sec_otp_hclk.common.hw,
+ [CLK_TRNG_PCLK] = &trng_pclk.common.hw,
+ [CLK_SEC_CRC_HCLK] = &sec_crc_hclk.common.hw,
+ [CLK_SMN_HCLK] = &rcpu_smn_hclk.common.hw,
+ [CLK_AHB0_HCLK] = &rcpu_ahb0_hclk.common.hw,
+ [CLK_SMN_PCLK] = &rcpu_smn_pclk.common.hw,
+ [CLK_SMN_CLK] = &rcpu_smn_clk.common.hw,
+ [CLK_SCRATCHPAD_CLK] = &rcpu_scratchpad_aclk.common.hw,
+ [CLK_RCPU_CORE_CLK] = &rcpu_core_clk.common.hw,
+ [CLK_RCPU_ROM_CLK] = &rcpu_rom_aclk.common.hw,
+ [CLK_OTP_LOAD_CLK] = &otp_load_clk.common.hw,
+ [CLK_NOC_PLL] = &nocc_pll_clk.common.hw,
+ [CLK_NOCC_CLK] = &nocc_clk_mux.common.hw,
+ [CLK_NOCC_DIV2] = &nocc_div2_clk.common.hw,
+ [CLK_NOCC_DIV4] = &nocc_div4_clk.common.hw,
+ [CLK_NOCC_RTC] = &nocc_rtc_clk.common.hw,
+ [CLK_NOCC_CAN] = &nocc_can_div.common.hw,
+ [CLK_QSPI_SCLK] = &qspi_sclk.common.hw,
+ [CLK_QSPI_HCLK] = &qspi_hclk.common.hw,
+ [CLK_I2C0_PCLK] = &i2c0_pclk.common.hw,
+ [CLK_I2C1_PCLK] = &i2c1_pclk.common.hw,
+ [CLK_I2C2_PCLK] = &i2c2_pclk.common.hw,
+ [CLK_I2C3_PCLK] = &i2c3_pclk.common.hw,
+ [CLK_I2C4_PCLK] = &i2c4_pclk.common.hw,
+ [CLK_UART0_PCLK] = &uart0_pclk.common.hw,
+ [CLK_UART1_PCLK] = &uart1_pclk.common.hw,
+ [CLK_UART2_PCLK] = &uart2_pclk.common.hw,
+ [CLK_UART3_PCLK] = &uart3_pclk.common.hw,
+ [CLK_UART4_PCLK] = &uart4_pclk.common.hw,
+ [CLK_SPI0_PCLK] = &spi0_pclk.common.hw,
+ [CLK_SPI1_PCLK] = &spi1_pclk.common.hw,
+ [CLK_SPI2_PCLK] = &spi2_pclk.common.hw,
+ [CLK_SPI3_PCLK] = &spi3_pclk.common.hw,
+ [CLK_GPIO_PCLK] = &gpio_pclk.common.hw,
+ [CLK_CAN0_HCLK] = &can0_hclk.common.hw,
+ [CLK_CAN0_CLK] = &can0_clk.common.hw,
+ [CLK_CAN1_HCLK] = &can1_hclk.common.hw,
+ [CLK_CAN1_CLK] = &can1_clk.common.hw,
+ [CLK_CAN0_TIMER_CLK] = &can0_timer_clk.common.hw,
+ [CLK_CAN1_TIMER_CLK] = &can1_timer_clk.common.hw,
+};
+
+static const struct atlantis_ccu_data atlantis_ccu_rcpu_data = {
+ .hws = atlantis_rcpu_clks,
+ .num = ARRAY_SIZE(atlantis_rcpu_clks),
+ .reset_name = "rcpu-reset"
+};
+
+static int atlantis_ccu_clocks_register(struct device *dev,
+ struct atlantis_ccu *ccu,
+ const struct atlantis_ccu_data *data)
+{
+ struct regmap *regmap = ccu->regmap;
+ struct clk_hw_onecell_data *clk_data;
+ int i, ret;
+ size_t num_clks = data->num;
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ ccu->clk_data = clk_data;
+
+ for (i = 0; i < data->num; i++) {
+ struct clk_hw *hw = data->hws[i];
+ const char *name = hw->init->name;
+ struct atlantis_clk_common *common =
+ hw_to_atlantis_clk_common(hw);
+ common->regmap = regmap;
+
+ ret = devm_clk_hw_register(dev, hw);
+
+ if (ret) {
+ dev_err(dev, "Cannot register clock %d - %s\n", i,
+ name);
+ return ret;
+ }
+
+ clk_data->hws[common->clkid] = hw;
+ }
+
+ clk_data->num = num_clks;
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
+ if (ret)
+ dev_err(dev, "failed to add clock hardware provider (%d)\n",
+ ret);
+
+ return ret;
+}
+
+static void atlantis_cadev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+
+ kfree(to_atlantis_ccu_adev(adev));
+}
+
+static void atlantis_adev_unregister(void *data)
+{
+ struct auxiliary_device *adev = data;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static int atlantis_ccu_adev_register(struct device *dev,
+ struct atlantis_ccu *ccu,
+ const struct atlantis_ccu_data *data,
+ const char *adev_name)
+{
+ struct atlantis_ccu_adev *cadev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
+ if (!cadev)
+ return -ENOMEM;
+
+ cadev->regmap = ccu->regmap;
+
+ adev = &cadev->adev;
+ adev->name = adev_name;
+ adev->dev.parent = dev;
+ adev->dev.release = atlantis_cadev_release;
+ adev->dev.of_node = dev->of_node;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ goto err_free_cadev;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(dev, atlantis_adev_unregister, adev);
+
+err_free_cadev:
+ kfree(cadev);
+
+ return ret;
+}
+static int atlantis_ccu_probe(struct platform_device *pdev)
+{
+ const struct atlantis_ccu_data *data;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ struct atlantis_ccu *ccu = devm_kzalloc(dev, sizeof(*ccu), GFP_KERNEL);
+
+ if (!ccu)
+ return -ENOMEM;
+
+ ccu->dev = dev;
+
+ ccu->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ccu->base))
+ return dev_err_probe(dev, PTR_ERR(ccu->base),
+ "Failed to map registers\n");
+
+ ccu->regmap = devm_regmap_init_mmio(dev, ccu->base,
+ &atlantis_ccu_regmap_config);
+ if (IS_ERR(ccu->regmap))
+ return dev_err_probe(dev, PTR_ERR(ccu->regmap),
+ "Failed to init regmap\n");
+
+ data = of_device_get_match_data(dev);
+
+ ret = atlantis_ccu_clocks_register(dev, ccu, data);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register clocks\n");
+
+ ret = atlantis_ccu_adev_register(dev, ccu, data, data->reset_name);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register resets\n");
+
+ return 0;
+}
+
+static const struct of_device_id atlantis_ccu_of_match[] = {
+ {
+ .compatible = "tenstorrent,atlantis-syscon-rcpu",
+ .data = &atlantis_ccu_rcpu_data,
+ },
+ {}
+
+};
+MODULE_DEVICE_TABLE(of, atlantis_ccu_of_match);
+
+static struct platform_driver atlantis_ccu_driver = {
+ .probe = atlantis_ccu_probe,
+ .driver = {
+ .name = "atlantis-ccu",
+ .of_match_table = atlantis_ccu_of_match,
+ },
+};
+module_platform_driver(atlantis_ccu_driver);
+
+MODULE_DESCRIPTION("Tenstorrent Atlantis Clock Controller Driver");
+MODULE_AUTHOR("Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>");
+MODULE_LICENSE("GPL");
diff --git a/include/soc/tenstorrent/atlantis-syscon.h b/include/soc/tenstorrent/atlantis-syscon.h
index 2c6387e5c21a..541b8c2f56c1 100644
--- a/include/soc/tenstorrent/atlantis-syscon.h
+++ b/include/soc/tenstorrent/atlantis-syscon.h
@@ -16,6 +16,17 @@ struct atlantis_ccu_adev {
#define to_atlantis_ccu_adev(_adev) \
container_of((_adev), struct atlantis_ccu_adev, adev)
+/* RCPU Clock Register Offsets */
+#define RCPU_PLL_CFG_REG 0x0000
+#define RCPU_NOCC_PLL_CFG_REG 0x0004
+#define RCPU_NOCC_CLK_CFG_REG 0x0008
+#define RCPU_DIV_CFG_REG 0x000C
+#define RCPU_BLK_CG_REG 0x0014
+#define LSIO_BLK_CG_REG 0x0018
+#define PLL_RCPU_EN_REG 0x011c
+#define PLL_NOCC_EN_REG 0x0120
+#define BUS_CG_REG 0x01FC
+
/* RCPU Reset Register Offsets */
#define RCPU_BLK_RST_REG 0x001c
#define LSIO_BLK_RST_REG 0x0020
@@ -23,4 +34,20 @@ struct atlantis_ccu_adev {
#define PCIE_SUBS_RST_REG 0x0000
#define MM_RSTN_REG 0x0014
+/* PLL Bit Definitions */
+#define PLL_CFG_EN_BIT BIT(0)
+#define PLL_CFG_BYPASS_BIT BIT(1)
+#define PLL_CFG_REFDIV_MASK GENMASK(7, 2)
+#define PLL_CFG_REFDIV_SHIFT 2
+#define PLL_CFG_POSTDIV1_MASK GENMASK(10, 8)
+#define PLL_CFG_POSTDIV1_SHIFT 8
+#define PLL_CFG_POSTDIV2_MASK GENMASK(13, 11)
+#define PLL_CFG_POSTDIV2_SHIFT 11
+#define PLL_CFG_FBDIV_MASK GENMASK(25, 14)
+#define PLL_CFG_FBDIV_SHIFT 14
+#define PLL_CFG_LKDT_BIT BIT(30)
+#define PLL_CFG_LOCK_BIT BIT(31)
+#define PLL_LOCK_TIMEOUT_US 1000
+#define PLL_BYPASS_WAIT_US 500
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver
2026-01-22 22:36 ` [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver Anirudh Srinivasan
@ 2026-01-23 7:03 ` kernel test robot
2026-01-23 11:41 ` kernel test robot
1 sibling, 0 replies; 11+ messages in thread
From: kernel test robot @ 2026-01-23 7:03 UTC (permalink / raw)
To: Anirudh Srinivasan, Drew Fustini, Joel Stanley, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Philipp Zabel
Cc: oe-kbuild-all, linux-riscv, devicetree, linux-kernel, linux-clk,
joel, fustini, mpe, mpe, npiggin, agross, agross, bmasney
Hi Anirudh,
kernel test robot noticed the following build errors:
[auto build test ERROR on 9448598b22c50c8a5bb77a9103e2d49f134c9578]
url: https://github.com/intel-lab-lkp/linux/commits/Anirudh-Srinivasan/dt-bindings-soc-tenstorrent-Add-tenstorrent-atlantis-syscon/20260123-064135
base: 9448598b22c50c8a5bb77a9103e2d49f134c9578
patch link: https://lore.kernel.org/r/20260122-atlantis-clocks-v2-3-c66371639e66%40oss.tenstorrent.com
patch subject: [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20260123/202601231402.YbzFbWJb-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260123/202601231402.YbzFbWJb-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601231402.YbzFbWJb-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/clk/tenstorrent/atlantis-ccu.c: In function 'atlantis_cadev_release':
>> drivers/clk/tenstorrent/atlantis-ccu.c:832:9: error: implicit declaration of function 'kfree' [-Wimplicit-function-declaration]
832 | kfree(to_atlantis_ccu_adev(adev));
| ^~~~~
drivers/clk/tenstorrent/atlantis-ccu.c: In function 'atlantis_ccu_adev_register':
>> drivers/clk/tenstorrent/atlantis-ccu.c:852:17: error: implicit declaration of function 'kzalloc' [-Wimplicit-function-declaration]
852 | cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
| ^~~~~~~
>> drivers/clk/tenstorrent/atlantis-ccu.c:852:15: error: assignment to 'struct atlantis_ccu_adev *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
852 | cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
| ^
vim +/kfree +832 drivers/clk/tenstorrent/atlantis-ccu.c
827
828 static void atlantis_cadev_release(struct device *dev)
829 {
830 struct auxiliary_device *adev = to_auxiliary_dev(dev);
831
> 832 kfree(to_atlantis_ccu_adev(adev));
833 }
834
835 static void atlantis_adev_unregister(void *data)
836 {
837 struct auxiliary_device *adev = data;
838
839 auxiliary_device_delete(adev);
840 auxiliary_device_uninit(adev);
841 }
842
843 static int atlantis_ccu_adev_register(struct device *dev,
844 struct atlantis_ccu *ccu,
845 const struct atlantis_ccu_data *data,
846 const char *adev_name)
847 {
848 struct atlantis_ccu_adev *cadev;
849 struct auxiliary_device *adev;
850 int ret;
851
> 852 cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
853 if (!cadev)
854 return -ENOMEM;
855
856 cadev->regmap = ccu->regmap;
857
858 adev = &cadev->adev;
859 adev->name = adev_name;
860 adev->dev.parent = dev;
861 adev->dev.release = atlantis_cadev_release;
862 adev->dev.of_node = dev->of_node;
863
864 ret = auxiliary_device_init(adev);
865 if (ret)
866 goto err_free_cadev;
867
868 ret = auxiliary_device_add(adev);
869 if (ret) {
870 auxiliary_device_uninit(adev);
871 return ret;
872 }
873
874 return devm_add_action_or_reset(dev, atlantis_adev_unregister, adev);
875
876 err_free_cadev:
877 kfree(cadev);
878
879 return ret;
880 }
881 static int atlantis_ccu_probe(struct platform_device *pdev)
882 {
883 const struct atlantis_ccu_data *data;
884 struct device *dev = &pdev->dev;
885 int ret;
886
887 struct atlantis_ccu *ccu = devm_kzalloc(dev, sizeof(*ccu), GFP_KERNEL);
888
889 if (!ccu)
890 return -ENOMEM;
891
892 ccu->dev = dev;
893
894 ccu->base = devm_platform_ioremap_resource(pdev, 0);
895 if (IS_ERR(ccu->base))
896 return dev_err_probe(dev, PTR_ERR(ccu->base),
897 "Failed to map registers\n");
898
899 ccu->regmap = devm_regmap_init_mmio(dev, ccu->base,
900 &atlantis_ccu_regmap_config);
901 if (IS_ERR(ccu->regmap))
902 return dev_err_probe(dev, PTR_ERR(ccu->regmap),
903 "Failed to init regmap\n");
904
905 data = of_device_get_match_data(dev);
906
907 ret = atlantis_ccu_clocks_register(dev, ccu, data);
908 if (ret)
909 return dev_err_probe(dev, ret, "failed to register clocks\n");
910
911 ret = atlantis_ccu_adev_register(dev, ccu, data, data->reset_name);
912 if (ret)
913 return dev_err_probe(dev, ret, "failed to register resets\n");
914
915 return 0;
916 }
917
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon
2026-01-22 22:36 ` [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon Anirudh Srinivasan
@ 2026-01-23 7:10 ` Krzysztof Kozlowski
2026-01-24 1:34 ` Anirudh Srinivasan
0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-23 7:10 UTC (permalink / raw)
To: Anirudh Srinivasan, Drew Fustini, Joel Stanley, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Philipp Zabel
Cc: linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
On 22/01/2026 23:36, Anirudh Srinivasan wrote:
> Document bindings for Tenstorrent Atlantis syscon that manages clocks
> and resets. This syscon block is instantiated 4 times in the SoC.
> This commit documents the clocks from the RCPU syscon block.
>
> Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
> ---
> .../tenstorrent/tenstorrent,atlantis-syscon.yaml | 90 ++++++++++++++++++
> MAINTAINERS | 2 +
> .../clock/tenstorrent,atlantis-syscon.h | 101 +++++++++++++++++++++
> 3 files changed, 193 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
> new file mode 100644
> index 000000000000..49fbe2423be0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tenstorrent Atlantis SoC Syscon
> +
> +maintainers:
> + - Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
> +
> +description:
> + Multifunctional register block found in Tenstorrent Atlantis SoC whose main function
> + is to control clocks and resets. This Block is instantiated multiple times in the SoC,
Please wrap code according to the preferred limit expressed in Kernel
coding style (checkpatch is not a coding style description, but only a
tool). However don't wrap blindly (see Kernel coding style).
> + each block controls clock and resets for a different subsystem.
> +
> + RCPU syscon serves low speed IO interfaces on chip
> + PCIe syscon serves all PCIe related functions
> + HSIO syscon serves high speed IO interfaces (Ethernet, USB)
> + MM syscon serves GPU, display and video processing functions
Same feedback - clock controllers go to clock, not soc.
> +
> +properties:
> + compatible:
> + enum:
> + - tenstorrent,atlantis-syscon-rcpu
> + - tenstorrent,atlantis-syscon-pcie
> + - tenstorrent,atlantis-syscon-mm
> + - tenstorrent,atlantis-syscon-hsio
Why do you call everything syscon? syscon is not a hardware name. How is
this exactly called in your datasheet?
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> + description:
> + See <dt-bindings/clock/tenstorrent,atlantis-syscon.h> for valid indices.
> +
> + "#reset-cells":
> + const: 1
> +
> + tenstorrent,syscon-rcpu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle reference to RCPU syscon, needed by other 3 syscons (PCIe, MM, HSIO)
> + as the control registers for the PLLs that drive these subsystems are in RCPU
> + syscon's range
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - tenstorrent,atlantis-syscon-pcie
> + - tenstorrent,atlantis-syscon-mm
> + - tenstorrent,atlantis-syscon-hsio
> + then:
> + required:
> + - tenstorrent,syscon-rcpu
else - properties false, see other examples how to do it.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon_rcpu: system-controller@a8000000 {
Drop entire example, one is enough.
> + compatible = "tenstorrent,atlantis-syscon-rcpu";
> + reg = <0xa8000000 0x10000>;
> + clocks = <&osc_24m>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> + - |
> + syscon_hsio: system-controller@e00c0000 {
Drop unused label.
> + compatible = "tenstorrent,atlantis-syscon-hsio";
> + reg = <0xe00c0000 0x500>;
> + clocks = <&osc_24m>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + tenstorrent,syscon-rcpu = <&syscon_rcpu>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index dc731d37c8fe..19a98b1fa456 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -22535,7 +22535,9 @@ L: linux-riscv@lists.infradead.org
> S: Maintained
> T: git https://github.com/tenstorrent/linux.git
> F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
> +F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
> F: arch/riscv/boot/dts/tenstorrent/
> +F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
>
> RISC-V THEAD SoC SUPPORT
> M: Drew Fustini <fustini@kernel.org>
> diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
> new file mode 100644
> index 000000000000..053cef2b43c8
> --- /dev/null
> +++ b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
Name will follow bindings.
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver
2026-01-22 22:36 ` [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver Anirudh Srinivasan
2026-01-23 7:03 ` kernel test robot
@ 2026-01-23 11:41 ` kernel test robot
1 sibling, 0 replies; 11+ messages in thread
From: kernel test robot @ 2026-01-23 11:41 UTC (permalink / raw)
To: Anirudh Srinivasan, Drew Fustini, Joel Stanley, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Philipp Zabel
Cc: llvm, oe-kbuild-all, linux-riscv, devicetree, linux-kernel,
linux-clk, joel, fustini, mpe, mpe, npiggin, agross, agross,
bmasney
Hi Anirudh,
kernel test robot noticed the following build errors:
[auto build test ERROR on 9448598b22c50c8a5bb77a9103e2d49f134c9578]
url: https://github.com/intel-lab-lkp/linux/commits/Anirudh-Srinivasan/dt-bindings-soc-tenstorrent-Add-tenstorrent-atlantis-syscon/20260123-064135
base: 9448598b22c50c8a5bb77a9103e2d49f134c9578
patch link: https://lore.kernel.org/r/20260122-atlantis-clocks-v2-3-c66371639e66%40oss.tenstorrent.com
patch subject: [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver
config: um-allmodconfig (https://download.01.org/0day-ci/archive/20260123/202601231918.PQTTcbRG-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260123/202601231918.PQTTcbRG-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601231918.PQTTcbRG-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/clk/tenstorrent/atlantis-ccu.c:12:
In file included from include/linux/regmap.h:20:
In file included from include/linux/iopoll.h:14:
In file included from include/linux/io.h:12:
In file included from arch/um/include/asm/io.h:24:
include/asm-generic/io.h:1209:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
1209 | return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
| ~~~~~~~~~~ ^
>> drivers/clk/tenstorrent/atlantis-ccu.c:832:2: error: call to undeclared function 'kfree'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
832 | kfree(to_atlantis_ccu_adev(adev));
| ^
>> drivers/clk/tenstorrent/atlantis-ccu.c:852:10: error: call to undeclared function 'kzalloc'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
852 | cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
| ^
>> drivers/clk/tenstorrent/atlantis-ccu.c:852:8: error: incompatible integer to pointer conversion assigning to 'struct atlantis_ccu_adev *' from 'int' [-Wint-conversion]
852 | cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/tenstorrent/atlantis-ccu.c:877:2: error: call to undeclared function 'kfree'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
877 | kfree(cadev);
| ^
1 warning and 4 errors generated.
vim +/kfree +832 drivers/clk/tenstorrent/atlantis-ccu.c
827
828 static void atlantis_cadev_release(struct device *dev)
829 {
830 struct auxiliary_device *adev = to_auxiliary_dev(dev);
831
> 832 kfree(to_atlantis_ccu_adev(adev));
833 }
834
835 static void atlantis_adev_unregister(void *data)
836 {
837 struct auxiliary_device *adev = data;
838
839 auxiliary_device_delete(adev);
840 auxiliary_device_uninit(adev);
841 }
842
843 static int atlantis_ccu_adev_register(struct device *dev,
844 struct atlantis_ccu *ccu,
845 const struct atlantis_ccu_data *data,
846 const char *adev_name)
847 {
848 struct atlantis_ccu_adev *cadev;
849 struct auxiliary_device *adev;
850 int ret;
851
> 852 cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
853 if (!cadev)
854 return -ENOMEM;
855
856 cadev->regmap = ccu->regmap;
857
858 adev = &cadev->adev;
859 adev->name = adev_name;
860 adev->dev.parent = dev;
861 adev->dev.release = atlantis_cadev_release;
862 adev->dev.of_node = dev->of_node;
863
864 ret = auxiliary_device_init(adev);
865 if (ret)
866 goto err_free_cadev;
867
868 ret = auxiliary_device_add(adev);
869 if (ret) {
870 auxiliary_device_uninit(adev);
871 return ret;
872 }
873
874 return devm_add_action_or_reset(dev, atlantis_adev_unregister, adev);
875
876 err_free_cadev:
877 kfree(cadev);
878
879 return ret;
880 }
881 static int atlantis_ccu_probe(struct platform_device *pdev)
882 {
883 const struct atlantis_ccu_data *data;
884 struct device *dev = &pdev->dev;
885 int ret;
886
887 struct atlantis_ccu *ccu = devm_kzalloc(dev, sizeof(*ccu), GFP_KERNEL);
888
889 if (!ccu)
890 return -ENOMEM;
891
892 ccu->dev = dev;
893
894 ccu->base = devm_platform_ioremap_resource(pdev, 0);
895 if (IS_ERR(ccu->base))
896 return dev_err_probe(dev, PTR_ERR(ccu->base),
897 "Failed to map registers\n");
898
899 ccu->regmap = devm_regmap_init_mmio(dev, ccu->base,
900 &atlantis_ccu_regmap_config);
901 if (IS_ERR(ccu->regmap))
902 return dev_err_probe(dev, PTR_ERR(ccu->regmap),
903 "Failed to init regmap\n");
904
905 data = of_device_get_match_data(dev);
906
907 ret = atlantis_ccu_clocks_register(dev, ccu, data);
908 if (ret)
909 return dev_err_probe(dev, ret, "failed to register clocks\n");
910
911 ret = atlantis_ccu_adev_register(dev, ccu, data, data->reset_name);
912 if (ret)
913 return dev_err_probe(dev, ret, "failed to register resets\n");
914
915 return 0;
916 }
917
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis
2026-01-22 22:36 ` [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis Anirudh Srinivasan
@ 2026-01-23 13:00 ` Philipp Zabel
2026-01-23 16:15 ` Anirudh Srinivasan
0 siblings, 1 reply; 11+ messages in thread
From: Philipp Zabel @ 2026-01-23 13:00 UTC (permalink / raw)
To: Anirudh Srinivasan, Drew Fustini, Joel Stanley, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd
Cc: linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
On Do, 2026-01-22 at 16:36 -0600, Anirudh Srinivasan wrote:
> Adds Atlantis Reset Controller and auxiliary device definitions for
> reset to share same regmap interface as clock controller.
>
> This version of the reset controller driver covers resets from the RCPU
> syscon.
>
> Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
> ---
> MAINTAINERS | 2 +
> drivers/reset/Kconfig | 11 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-tenstorrent-atlantis.c | 158 +++++++++++++++++++++++++++++
> include/soc/tenstorrent/atlantis-syscon.h | 26 +++++
> 5 files changed, 198 insertions(+)
>
[...]
> diff --git a/drivers/reset/reset-tenstorrent-atlantis.c b/drivers/reset/reset-tenstorrent-atlantis.c
> new file mode 100644
> index 000000000000..2e7f09409f79
> --- /dev/null
> +++ b/drivers/reset/reset-tenstorrent-atlantis.c
> @@ -0,0 +1,158 @@
[...]
> +static int atlantis_reset_update(struct reset_controller_dev *rcdev,
> + unsigned long id, bool assert)
> +{
> + unsigned int val;
> + struct atlantis_reset_controller *rst =
> + to_atlantis_reset_controller(rcdev);
> + const struct atlantis_reset_data *data = &rst->data->reset_data[id];
> + unsigned int mask = BIT(data->bit);
> + struct regmap *regmap = rst->regmap;
> +
> + if (data->active_low ^ assert)
> + val = mask;
> + else
> + val = ~mask;
val = 0;
The ~mask bits will be ignored anyway.
[...]
> diff --git a/include/soc/tenstorrent/atlantis-syscon.h b/include/soc/tenstorrent/atlantis-syscon.h
> new file mode 100644
> index 000000000000..2c6387e5c21a
> --- /dev/null
> +++ b/include/soc/tenstorrent/atlantis-syscon.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2026 Tenstorrent
> + */
> +#ifndef __SOC_ATLANTIS_SYSCON_H__
> +#define __SOC_ATLANTIS_SYSCON_H__
> +
> +#include <linux/bits.h>
> +#include <linux/types.h>
#include <linux/auxiliary_bus.h>
struct regmap;
> +
> +struct atlantis_ccu_adev {
> + struct auxiliary_device adev;
> + struct regmap *regmap;
> +};
> +
> +#define to_atlantis_ccu_adev(_adev) \
> + container_of((_adev), struct atlantis_ccu_adev, adev)
Please use an inline function instead of a macro.
> +
> +/* RCPU Reset Register Offsets */
> +#define RCPU_BLK_RST_REG 0x001c
> +#define LSIO_BLK_RST_REG 0x0020
> +#define HSIO_BLK_RST_REG 0x000c
> +#define PCIE_SUBS_RST_REG 0x0000
> +#define MM_RSTN_REG 0x0014
Why not move these into reset-tenstorrent-atlantis.c, they are not part
of the interface between clock and reset drivers.
regards
Philipp
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis
2026-01-23 13:00 ` Philipp Zabel
@ 2026-01-23 16:15 ` Anirudh Srinivasan
2026-01-26 7:23 ` Philipp Zabel
0 siblings, 1 reply; 11+ messages in thread
From: Anirudh Srinivasan @ 2026-01-23 16:15 UTC (permalink / raw)
To: Philipp Zabel
Cc: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, linux-riscv,
devicetree, linux-kernel, linux-clk, joel, fustini, mpe, mpe,
npiggin, agross, agross, bmasney
Hi Philipp,
On Fri, Jan 23, 2026 at 7:00 AM Philipp Zabel <p.zabel@pengutronix.de> wrote:
>
> On Do, 2026-01-22 at 16:36 -0600, Anirudh Srinivasan wrote:
> > Adds Atlantis Reset Controller and auxiliary device definitions for
> > reset to share same regmap interface as clock controller.
> >
> > + if (data->active_low ^ assert)
> > + val = mask;
> > + else
> > + val = ~mask;
>
> val = 0;
>
> The ~mask bits will be ignored anyway.
Ack. Will change.
>
> struct regmap;
>
> > +
> > +struct atlantis_ccu_adev {
> > + struct auxiliary_device adev;
> > + struct regmap *regmap;
> > +};
> > +
> > +#define to_atlantis_ccu_adev(_adev) \
> > + container_of((_adev), struct atlantis_ccu_adev, adev)
>
> Please use an inline function instead of a macro.
Ack.
>
> > +
> > +/* RCPU Reset Register Offsets */
> > +#define RCPU_BLK_RST_REG 0x001c
> > +#define LSIO_BLK_RST_REG 0x0020
> > +#define HSIO_BLK_RST_REG 0x000c
> > +#define PCIE_SUBS_RST_REG 0x0000
> > +#define MM_RSTN_REG 0x0014
>
> Why not move these into reset-tenstorrent-atlantis.c, they are not part
> of the interface between clock and reset drivers.
We were considering putting register offsets like this in separate
header files that are dual licensed. In that case, is it okay to put
it here?
>
> regards
> Philipp
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon
2026-01-23 7:10 ` Krzysztof Kozlowski
@ 2026-01-24 1:34 ` Anirudh Srinivasan
0 siblings, 0 replies; 11+ messages in thread
From: Anirudh Srinivasan @ 2026-01-24 1:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Philipp Zabel,
linux-riscv, devicetree, linux-kernel, linux-clk, joel, fustini,
mpe, mpe, npiggin, agross, agross, bmasney
Hi Krzysztof,
On Fri, Jan 23, 2026 at 1:10 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 22/01/2026 23:36, Anirudh Srinivasan wrote:
> > Document bindings for Tenstorrent Atlantis syscon that manages clocks
> > and resets. This syscon block is instantiated 4 times in the SoC.
> > This commit documents the clocks from the RCPU syscon block.
> > diff --git a/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
> > new file mode 100644
> > index 000000000000..49fbe2423be0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
> > +description:
> > + Multifunctional register block found in Tenstorrent Atlantis SoC whose main function
> > + is to control clocks and resets. This Block is instantiated multiple times in the SoC,
>
> Please wrap code according to the preferred limit expressed in Kernel
> coding style (checkpatch is not a coding style description, but only a
> tool). However don't wrap blindly (see Kernel coding style).
Ack.
>
> > + each block controls clock and resets for a different subsystem.
> > +
> > + RCPU syscon serves low speed IO interfaces on chip
> > + PCIe syscon serves all PCIe related functions
> > + HSIO syscon serves high speed IO interfaces (Ethernet, USB)
> > + MM syscon serves GPU, display and video processing functions
>
> Same feedback - clock controllers go to clock, not soc.
>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - tenstorrent,atlantis-syscon-rcpu
> > + - tenstorrent,atlantis-syscon-pcie
> > + - tenstorrent,atlantis-syscon-mm
> > + - tenstorrent,atlantis-syscon-hsio
>
> Why do you call everything syscon? syscon is not a hardware name. How is
> this exactly called in your datasheet?
I picked the syscon name since the block is a bunch of registers that
control different functions in the SoC. The block's name in the
datasheet is PRCM, so I will stick to that name and treat this node as
a clock controller as its main functionality is that.
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - tenstorrent,atlantis-syscon-pcie
> > + - tenstorrent,atlantis-syscon-mm
> > + - tenstorrent,atlantis-syscon-hsio
> > + then:
> > + required:
> > + - tenstorrent,syscon-rcpu
>
> else - properties false, see other examples how to do it.
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + syscon_rcpu: system-controller@a8000000 {
>
> Drop entire example, one is enough.
>
> > + compatible = "tenstorrent,atlantis-syscon-rcpu";
> > + reg = <0xa8000000 0x10000>;
> > + clocks = <&osc_24m>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > + - |
> > + syscon_hsio: system-controller@e00c0000 {
>
> Drop unused label.
Ack.
> > diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
> > new file mode 100644
> > index 000000000000..053cef2b43c8
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
>
> Name will follow bindings.
Ack
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis
2026-01-23 16:15 ` Anirudh Srinivasan
@ 2026-01-26 7:23 ` Philipp Zabel
0 siblings, 0 replies; 11+ messages in thread
From: Philipp Zabel @ 2026-01-26 7:23 UTC (permalink / raw)
To: Anirudh Srinivasan
Cc: Drew Fustini, Joel Stanley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, linux-riscv,
devicetree, linux-kernel, linux-clk, joel, fustini, mpe, mpe,
npiggin, agross, agross, bmasney
On Fr, 2026-01-23 at 10:15 -0600, Anirudh Srinivasan wrote:
> > > +/* RCPU Reset Register Offsets */
> > > +#define RCPU_BLK_RST_REG 0x001c
> > > +#define LSIO_BLK_RST_REG 0x0020
> > > +#define HSIO_BLK_RST_REG 0x000c
> > > +#define PCIE_SUBS_RST_REG 0x0000
> > > +#define MM_RSTN_REG 0x0014
> >
> > Why not move these into reset-tenstorrent-atlantis.c, they are not part
> > of the interface between clock and reset drivers.
>
> We were considering putting register offsets like this in separate
> header files that are dual licensed. In that case, is it okay to put
> it here?
I see, nothing wrong with that.
regards
Philipp
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2026-01-26 7:23 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-22 22:36 [PATCH v2 0/3] Add Tenstorrent Atlantis Clock/Reset Controller Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon Anirudh Srinivasan
2026-01-23 7:10 ` Krzysztof Kozlowski
2026-01-24 1:34 ` Anirudh Srinivasan
2026-01-22 22:36 ` [PATCH v2 2/3] reset: tenstorrent: Add reset controller for Atlantis Anirudh Srinivasan
2026-01-23 13:00 ` Philipp Zabel
2026-01-23 16:15 ` Anirudh Srinivasan
2026-01-26 7:23 ` Philipp Zabel
2026-01-22 22:36 ` [PATCH v2 3/3] clk: tenstorrent: Add Atlantis clock controller driver Anirudh Srinivasan
2026-01-23 7:03 ` kernel test robot
2026-01-23 11:41 ` kernel test robot
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