From: Rob Herring <robh@kernel.org>
To: John Madieu <john.madieu.xa@bp.renesas.com>
Cc: claudiu.beznea.uj@bp.renesas.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, geert+renesas@glider.be,
krzk+dt@kernel.org, bhelgaas@google.com, conor+dt@kernel.org,
magnus.damm@gmail.com, biju.das.jz@bp.renesas.com,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
john.madieu@gmail.com
Subject: Re: [PATCH v2 06/15] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
Date: Mon, 26 Jan 2026 08:31:14 -0600 [thread overview]
Message-ID: <20260126143114.GA2223879-robh@kernel.org> (raw)
In-Reply-To: <20260123140031.94752-7-john.madieu.xa@bp.renesas.com>
On Fri, Jan 23, 2026 at 03:00:22PM +0100, John Madieu wrote:
> Extend the existing device tree bindings for Renesas RZ/G3S PCIe
> controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
> controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
> differences:
>
> - Uses a different device ID
> - Supports PCIe Gen3 (8.0 GT/s) link speeds
> - Uses a different clock naming (clkpmu vs clkl1pm)
> - Has a different set of interrupts, interrupt ordering, and reset signals
>
> Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>
> Changes:
>
> v2: Reuse G3S names
>
> .../bindings/pci/renesas,r9a08g045-pcie.yaml | 127 +++++++++++++-----
> 1 file changed, 96 insertions(+), 31 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> index df30f729d4b3..9565f1774720 100644
> --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> @@ -10,17 +10,21 @@ maintainers:
> - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> description:
> - Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
> - 4.0 and supports up to 5 GT/s (Gen2).
> + Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
> + Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
> + up to 8 GT/s (Gen3) for RZ/G3E.
>
> properties:
> compatible:
> - const: renesas,r9a08g045-pcie # RZ/G3S
> + enum:
> + - renesas,r9a08g045-pcie # RZ/G3S
> + - renesas,r9a09g047-pcie # RZ/G3E
>
> reg:
> maxItems: 1
>
> interrupts:
> + minItems: 16
> items:
> - description: System error interrupt
> - description: System error on correctable error interrupt
> @@ -38,39 +42,54 @@ properties:
> - description: PCIe event interrupt
> - description: Message interrupt
> - description: All interrupts
> + - description: Link equalization request interrupt
> + - description: Turn off event interrupt
> + - description: PMU power off interrupt
> + - description: D3 event function 0 interrupt
> + - description: D3 event function 1 interrupt
> + - description: Configuration PMCSR write clear function 0 interrupt
> + - description: Configuration PMCSR write clear function 1 interrupt
>
> interrupt-names:
> + minItems: 16
> items:
> - - description: serr
> - - description: serr_cor
> - - description: serr_nonfatal
> - - description: serr_fatal
> - - description: axi_err
> - - description: inta
> - - description: intb
> - - description: intc
> - - description: intd
> - - description: msi
> - - description: link_bandwidth
> - - description: pm_pme
> - - description: dma
> - - description: pcie_evt
> - - description: msg
> - - description: all
Well, that was really wrong... Fixing it should be a separate patch
before adding the new chip.
> + - const: serr
> + - const: serr_cor
> + - const: serr_nonfatal
> + - const: serr_fatal
> + - const: axi_err
> + - const: inta
> + - const: intb
> + - const: intc
> + - const: intd
> + - const: msi
> + - const: link_bandwidth
> + - const: pm_pme
> + - const: dma
> + - const: pcie_evt
> + - const: msg
> + - const: all
> + - const: link_equalization_request
> + - const: turn_off_event
> + - const: pmu_poweroff
> + - const: d3_event_f0
> + - const: d3_event_f1
> + - const: cfg_pmcsr_writeclear_f0
> + - const: cfg_pmcsr_writeclear_f1
>
> interrupt-controller: true
>
> clocks:
> + minItems: 2
> items:
> - description: System clock
> - description: PM control clock
> + - description: PMU clock
I don't see 3 clocks being valid.
>
> - clock-names:
> - items:
> - - description: aclk
> - - description: pm
> + clock-names: true
This should keep at least minItems/maxItems constraints.
> + clock-names:
> + items:
> + - const: aclk
> + - const: pm
> + clock-names:
> + items:
> + - const: aclk
> + - const: pmu
pm vs. pmu? Are these really different? The "P" here is never defined.
If it is always "power", then use the same name.
Rob
next prev parent reply other threads:[~2026-01-26 14:31 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-23 14:00 [PATCH v2 00/15] PCI: renesas: Add RZ/G3E PCIe controller support John Madieu
2026-01-23 14:00 ` [PATCH v2 01/15] PCI: rzg3s-host: Fix reset handling in probe error path John Madieu
2026-01-23 14:00 ` [PATCH v2 02/15] PCI: renesas: rzg3s: Rework inbound window algorithm for multi-SoC support John Madieu
2026-01-23 14:00 ` [PATCH v2 03/15] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets John Madieu
2026-01-23 14:42 ` Geert Uytterhoeven
2026-01-23 14:00 ` [PATCH v2 04/15] clk: renesas: r9a09g047: Add PCIe clocks and reset John Madieu
2026-01-23 14:36 ` Geert Uytterhoeven
2026-01-23 14:00 ` [PATCH v2 05/15] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix typo in interrupt-names John Madieu
2026-01-23 14:17 ` Geert Uytterhoeven
2026-01-23 14:36 ` John Madieu
2026-01-23 14:00 ` [PATCH v2 06/15] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC John Madieu
2026-01-23 14:22 ` Biju Das
2026-01-23 15:16 ` John Madieu
2026-01-23 15:38 ` Rob Herring (Arm)
2026-01-26 14:31 ` Rob Herring [this message]
2026-01-26 16:46 ` John Madieu
2026-01-26 16:55 ` Biju Das
2026-01-23 14:00 ` [PATCH v2 07/15] PCI: rzg3s-host: Make SYSC register offsets SoC-specific John Madieu
2026-01-23 14:00 ` [PATCH v2 08/15] PCI: rzg3s-host: Make configuration reset lines optional John Madieu
2026-01-23 14:00 ` [PATCH v2 09/15] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks John Madieu
2026-01-23 14:00 ` [PATCH v2 10/15] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility John Madieu
2026-01-23 14:00 ` [PATCH v2 11/15] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support John Madieu
2026-01-23 14:00 ` [PATCH v2 12/15] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller John Madieu
2026-01-23 14:00 ` [PATCH v2 13/15] arm64: dts: renesas: r9a09g047: Add PCIe node John Madieu
2026-01-23 14:00 ` [PATCH v2 14/15] arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock John Madieu
2026-01-23 14:00 ` [PATCH v2 15/15] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe John Madieu
2026-01-23 14:20 ` Biju Das
2026-01-23 16:54 ` John Madieu
2026-01-23 17:02 ` Biju Das
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