From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0C57284883; Tue, 27 Jan 2026 14:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769523461; cv=none; b=UvucbLqOxQ8ZHhD5lPd1aXIZJMnieiEx8Y9YrTWM2Lb7KNVi7dOf/Y2TmlVxFy5MfF5s8mA3xHtR7XF9O9vbdchP6eLuX1PzElblX7QvEIaXOubE9/diQ2mi0CUz/44ZzRgXntgniSZVKNIMm+yhPTdGZ+MOvccXV+xB8DS1Zso= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769523461; c=relaxed/simple; bh=6RbS3lq83MUvqvXbpS/fqmTiQO3rUelLTxFVy+AhT9w=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sYDAqERyRWbx1h4419Fufmuuyov5y8QMUWfyCPF7YZMMtYOdA3/hILrltTqe4Cz3CHIj2wEfKlwyUmI+1zjkatdtQM74mnFJjfnBG8tr4BDbXcu3ktOqcxptxt9HnLlLIS861LuVRJ7YrsRLFKKVVz59IqPGSKkDlA4tqNx0NtQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Qjmw469Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Qjmw469Q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 878A7C116C6; Tue, 27 Jan 2026 14:17:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769523461; bh=6RbS3lq83MUvqvXbpS/fqmTiQO3rUelLTxFVy+AhT9w=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Qjmw469Qb8tRmK1hTgMyz5TmDgi2kY/hL8sEeYWOIYG4jrJeBle28BKtG/TuBC+Go eTSTVc8XnRjIc59p4lgv7geyu62HnwlQYS+ABiW0WtEx/7d7qnHjQfMrVRMl9VGXxi K9kCvkMEBBNARtpyTYIXQ6cXrEaOPUbX9K0jRCvlagc6q4rsv1XtjD7rsbHvH3yiID PdFnD63XkcOtbjpXnSh59ihd7BCxFahLg5JaIuGsg4Y+vjEUrjROebHQnvC36X7Pt8 eLLWzKPk9hbs6lzKwsDu/tf26YQ52Deluy3LXaNAaeYlQG0B0648tAcoj6fx7osS2X KdRqplkHn5nJw== Date: Tue, 27 Jan 2026 08:17:40 -0600 From: Rob Herring To: Mohammad Rafi Shaik Cc: Bjorn Andersson , Linus Walleij , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] dt-bindings: pinctrl: qcom,sm8450-lpass-lpi-pinctrl: Add SA8775P and QCS8300 pinctrl Message-ID: <20260127141740.GA1574044-robh@kernel.org> References: <20260127105511.3917491-1-mohammad.rafi.shaik@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260127105511.3917491-1-mohammad.rafi.shaik@oss.qualcomm.com> On Tue, Jan 27, 2026 at 04:25:11PM +0530, Mohammad Rafi Shaik wrote: > Document compatible for Qualcomm SA8775P and QCS8300 SoC LPASS TLMM > pin controller, fully compatible with previous SM8450 generation > (same amount of pins and functions). > > Signed-off-by: Mohammad Rafi Shaik > --- > changes in [v3]: > - Removed the duplicate driver code patch as suggested by Krzysztof. > - Reused the existing SM8490 pinctrl, which is fully compatible with SA8775P and QCS8300. > - Link to V2: https://lore.kernel.org/all/20260107192007.500995-1-mohammad.rafi.shaik@oss.qualcomm.com/ > > changes in [v2]: > - Fixed dt-binding errors reported by Krzysztof and Rob. > - Added proper slew rate value for wsa2_swr_data GPIO, as suggested by Konrad. > - Documented Monaco compatible as suggested by Konrad. > - Link to V1: https://lore.kernel.org/all/20251116171656.3105461-1-mohammad.rafi.shaik@oss.qualcomm.com/ > --- > .../pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml > index e7565592d..354629c38 100644 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml > @@ -15,7 +15,15 @@ description: > > properties: > compatible: > - const: qcom,sm8450-lpass-lpi-pinctrl > + oneOf: > + - const: qcom,sm8450-lpass-lpi-pinctrl > + - items: > + - enum: > + - qcom,qcs8300-lpass-lpi-pinctrl > + - qcom,sa8775p-lpass-lpi-pinctrl > + - const: qcom,sm8450-lpass-lpi-pinctrl > + minItems: 1 > + maxItems: 2 No. You are either backwards compatible with sm8450 or you aren't. The h/w is fixed. Rob