Re: [PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Conor Dooley <conor@kernel.org>]

[-- Attachment #1: Type: text/plain, Size: 1453 bytes --]

On Sat, Jan 31, 2026 at 11:28:56AM -0600, Dinh Nguyen wrote:
> From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> 
> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> operates on a cache-coherent AXI interface, where DMA transactions are
> automatically kept coherent with the CPU caches. In previous generations
> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> is no need for dma-coherent property to be presence. In Agilex 5, the
> architecture has changed. It  introduced a coherent interconnect that
> supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Why does this v1 have an ack?

> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 216cda21c538..e12a48a12ea4 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -68,6 +68,8 @@ properties:
>  
>    dma-noncoherent: true
>  
> +  dma-coherent: true
> +
>    resets:
>      minItems: 1
>      maxItems: 2
> -- 
> 2.42.0.411.g813d9a9188
> 
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]