From: Dinh Nguyen <dinguyen@kernel.org>
To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com
Cc: dinguyen@kernel.org, linux-mtd@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Khairul Anuar Romli <khairul.anuar.romli@altera.com>,
Rob Herring <robh@kernel.org>
Subject: [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
Date: Sat, 31 Jan 2026 11:26:11 -0600 [thread overview]
Message-ID: <20260131172611.28807-1-dinguyen@kernel.org> (raw)
From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
The Cadence HP NAND Flash Controller on supports DMA transactions through
a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
the interconnect was non-coherent, hence there is no need for dma-coherent
property to be presence. In Agilex 5, the architecture has changed. It
introduced a coherent interconnect that supports cache-coherent DMA.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index 73dc69cee4d8..367257a227b1 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,8 @@ properties:
dmas:
maxItems: 1
+ dma-coherent: true
+
iommus:
maxItems: 1
--
2.42.0.411.g813d9a9188
next reply other threads:[~2026-01-31 17:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-31 17:26 Dinh Nguyen [this message]
2026-01-31 20:26 ` [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property Conor Dooley
2026-02-01 19:25 ` Dinh Nguyen
2026-02-03 16:15 ` Miquel Raynal
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