[PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Dinh Nguyen]

From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>

The Cadence HP NAND Flash Controller on supports DMA transactions through
a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
the interconnect was non-coherent, hence there is no need for dma-coherent
property to be presence. In Agilex 5, the architecture has changed. It
introduced a coherent interconnect that supports cache-coherent DMA.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index 73dc69cee4d8..367257a227b1 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,8 @@ properties:
   dmas:
     maxItems: 1
 
+  dma-coherent: true
+
   iommus:
     maxItems: 1
 
-- 
2.42.0.411.g813d9a9188

Re: [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1314 bytes --]

On Sat, Jan 31, 2026 at 11:26:11AM -0600, Dinh Nguyen wrote:
> From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> 
> The Cadence HP NAND Flash Controller on supports DMA transactions through
> a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
> the interconnect was non-coherent, hence there is no need for dma-coherent
> property to be presence. In Agilex 5, the architecture has changed. It
> introduced a coherent interconnect that supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Why does this v1 have an ack?

> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
> index 73dc69cee4d8..367257a227b1 100644
> --- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
> +++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
> @@ -40,6 +40,8 @@ properties:
>    dmas:
>      maxItems: 1
>  
> +  dma-coherent: true
> +
>    iommus:
>      maxItems: 1
>  
> -- 
> 2.42.0.411.g813d9a9188
> 
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Dinh Nguyen]

On 1/31/26 14:26, Conor Dooley wrote:
> On Sat, Jan 31, 2026 at 11:26:11AM -0600, Dinh Nguyen wrote:
>> From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>
>> The Cadence HP NAND Flash Controller on supports DMA transactions through
>> a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
>> the interconnect was non-coherent, hence there is no need for dma-coherent
>> property to be presence. In Agilex 5, the architecture has changed. It
>> introduced a coherent interconnect that supports cache-coherent DMA.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> 
> Why does this v1 have an ack?
> 

I respun this patch based on the mtd tree so that the mtd maintainers 
can take it. I had originally applied it to my tree, but avoid merge 
conflicts, I'm going to submit it through mtd. This patch is the same as 
this[1].

Sorry for any confusion.

Dinh
[1] 
https://lore.kernel.org/linux-devicetree/176488419217.2206248.9983976146883123306.robh@kernel.org/

Re: [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Miquel Raynal]

On Sat, 31 Jan 2026 11:26:11 -0600, Dinh Nguyen wrote:
> The Cadence HP NAND Flash Controller on supports DMA transactions through
> a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
> the interconnect was non-coherent, hence there is no need for dma-coherent
> property to be presence. In Agilex 5, the architecture has changed. It
> introduced a coherent interconnect that supports cache-coherent DMA.
> 
> 
> [...]

Applied to mtd/next, thanks!

[1/1] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
      commit: 875382759298650c96192bf2c12e2d1e4575de92

Patche(s) should be available on mtd/linux.git and will be
part of the next PR (provided that no robot complains by then).

Kind regards,
Miquèl