[PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Dinh Nguyen]

From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>

The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
operates on a cache-coherent AXI interface, where DMA transactions are
automatically kept coherent with the CPU caches. In previous generations
SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
is no need for dma-coherent property to be presence. In Agilex 5, the
architecture has changed. It  introduced a coherent interconnect that
supports cache-coherent DMA.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 216cda21c538..e12a48a12ea4 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -68,6 +68,8 @@ properties:
 
   dma-noncoherent: true
 
+  dma-coherent: true
+
   resets:
     minItems: 1
     maxItems: 2
-- 
2.42.0.411.g813d9a9188

Re: [PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Conor Dooley]

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On Sat, Jan 31, 2026 at 11:28:56AM -0600, Dinh Nguyen wrote:
> From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> 
> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> operates on a cache-coherent AXI interface, where DMA transactions are
> automatically kept coherent with the CPU caches. In previous generations
> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> is no need for dma-coherent property to be presence. In Agilex 5, the
> architecture has changed. It  introduced a coherent interconnect that
> supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Why does this v1 have an ack?

> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 216cda21c538..e12a48a12ea4 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -68,6 +68,8 @@ properties:
>  
>    dma-noncoherent: true
>  
> +  dma-coherent: true
> +
>    resets:
>      minItems: 1
>      maxItems: 2
> -- 
> 2.42.0.411.g813d9a9188
> 
> 

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Re: [PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Dinh Nguyen]

On 1/31/26 14:27, Conor Dooley wrote:
> On Sat, Jan 31, 2026 at 11:28:56AM -0600, Dinh Nguyen wrote:
>> From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>
>> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
>> operates on a cache-coherent AXI interface, where DMA transactions are
>> automatically kept coherent with the CPU caches. In previous generations
>> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
>> is no need for dma-coherent property to be presence. In Agilex 5, the
>> architecture has changed. It  introduced a coherent interconnect that
>> supports cache-coherent DMA.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> 
> Why does this v1 have an ack?
> 

I respun this patch based on the dmaengine tree so that the dma engine 
maintainer can take it. I had originally applied it to my tree, but 
avoid potential merge conflicts, I'm going to submit it through dma. 
This patch is the same as this[1].

Sorry for any confusion.

Dinh
[1] 
https://lore.kernel.org/linux-devicetree/176488420978.2206697.11201292177123636920.robh@kernel.org/

Re: [PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Conor Dooley]

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On Sun, Feb 01, 2026 at 01:30:59PM -0600, Dinh Nguyen wrote:
> 
> 
> On 1/31/26 14:27, Conor Dooley wrote:
> > On Sat, Jan 31, 2026 at 11:28:56AM -0600, Dinh Nguyen wrote:
> > > From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> > > 
> > > The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> > > operates on a cache-coherent AXI interface, where DMA transactions are
> > > automatically kept coherent with the CPU caches. In previous generations
> > > SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> > > is no need for dma-coherent property to be presence. In Agilex 5, the
> > > architecture has changed. It  introduced a coherent interconnect that
> > > supports cache-coherent DMA.
> > > 
> > > Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> > > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> > 
> > Why does this v1 have an ack?
> > 
> 
> I respun this patch based on the dmaengine tree so that the dma engine
> maintainer can take it. I had originally applied it to my tree, but avoid
> potential merge conflicts, I'm going to submit it through dma. This patch is
> the same as this[1].

In the future, please note this or carry on the version number from the
series it was originally in.

> 
> Sorry for any confusion.
> 
> Dinh
> [1] https://lore.kernel.org/linux-devicetree/176488420978.2206697.11201292177123636920.robh@kernel.org/

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Re: [PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Vinod Koul]

On Sat, 31 Jan 2026 11:28:56 -0600, Dinh Nguyen wrote:
> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> operates on a cache-coherent AXI interface, where DMA transactions are
> automatically kept coherent with the CPU caches. In previous generations
> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> is no need for dma-coherent property to be presence. In Agilex 5, the
> architecture has changed. It  introduced a coherent interconnect that
> supports cache-coherent DMA.
> 
> [...]

Applied, thanks!

[1/1] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
      commit: ff7cbcca2b32c6e079941e577c41c74036861d5a

Best regards,
-- 
~Vinod