* [PATCH 0/8] phy: zynqmp: Perform complete initialization, including ILL calibration @ 2026-02-03 0:21 Sean Anderson 2026-02-03 0:21 ` [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets Sean Anderson 0 siblings, 1 reply; 6+ messages in thread From: Sean Anderson @ 2026-02-03 0:21 UTC (permalink / raw) To: Laurent Pinchart, Vinod Koul, linux-phy Cc: Krzysztof Wilczyński, Lorenzo Pieralisi, Radhey Shyam Pandey, linux-kernel, Michal Simek, linux-arm-kernel, linux-pci, Neil Armstrong, Rob Herring, Thippeswamy Havalige, Manivannan Sadhasivam, Bjorn Helgaas, Sean Anderson, Conor Dooley, Krzysztof Kozlowski, devicetree This series completely initializes the GTRs in Linux, making all bootloader initialization (as performed by init_serdes() in psu_init_gpl.c) optional. This gives the following advantages: - On some boards (mine) the reference clocks may not be configured in SPL/FSBL. So ILL calibration will fail (and take a long time to do so) unless we defer initialization to U-Boot/Linux where the phy driver can request the clocks. - If PCIe/SATA are not used in U-Boot, ILL calibration can be deferred until Linux when it can be done it parallel with other initialization. - We will have flexibility to switch between different configurations at runtime. For example, this could allow supporting both SATA and PCIe M.2 cards with [1]. I have tested this series with DP, PCIe, SGMII, and SATA. USB3 is broken on my dev board at the moment (independent of this series; need to investigate) so I have not tested that. I have an equivalent set of patches for U-Boot that I will try to post soon. [1] https://lore.kernel.org/linux-pci/20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com/ Sean Anderson (8): dt-bindings: pci: xilinx-nwl: Add resets phy: zynqmp: Refactor bus width configuration into helper phy: zynqmp: Refactor common phy initialization into a helper phy: zynqmp: Calibrate ILL if necessary phy: zynqmp: Initialize chicken bits PCI: xilinx-nwl: Split phy_init from phy_power_on PCI: xilinx-nwl: Reset the core during probe arm64: zynqmp: Add PCIe resets .../bindings/pci/xlnx,nwl-pcie.yaml | 17 + arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 + drivers/pci/controller/pcie-xilinx-nwl.c | 255 +++++++-- drivers/phy/xilinx/phy-zynqmp.c | 487 +++++++++++++++++- 4 files changed, 713 insertions(+), 50 deletions(-) -- 2.35.1.1320.gc452695387.dirty ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets 2026-02-03 0:21 [PATCH 0/8] phy: zynqmp: Perform complete initialization, including ILL calibration Sean Anderson @ 2026-02-03 0:21 ` Sean Anderson 2026-02-04 8:32 ` Pandey, Radhey Shyam 2026-02-10 0:24 ` Rob Herring (Arm) 0 siblings, 2 replies; 6+ messages in thread From: Sean Anderson @ 2026-02-03 0:21 UTC (permalink / raw) To: Laurent Pinchart, Vinod Koul, linux-phy Cc: Krzysztof Wilczyński, Lorenzo Pieralisi, Radhey Shyam Pandey, linux-kernel, Michal Simek, linux-arm-kernel, linux-pci, Neil Armstrong, Rob Herring, Thippeswamy Havalige, Manivannan Sadhasivam, Bjorn Helgaas, Sean Anderson, Conor Dooley, Krzysztof Kozlowski, devicetree Add resets so we can hold the bridge in reset while we perform phy calibration. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> --- .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 9de3c09efb6e..7efb3dd9955f 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -69,6 +69,18 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 3 + + reset-names: + items: + - description: APB register block reset + const: cfg + - description: AXI-PCIe bridge reset + const: bridge + - description: PCIe MAC reset + const: ctrl + iommus: maxItems: 1 @@ -117,6 +129,7 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> + #include <dt-bindings/reset/xlnx-zynqmp-resets.h> soc { #address-cells = <2>; #size-cells = <2>; @@ -146,6 +159,10 @@ examples: msi-parent = <&nwl_pcie>; phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; power-domains = <&zynqmp_firmware PD_PCIE>; + resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>, + <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>, + <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>; + reset-names = "cfg", "bridge", "ctrl"; iommus = <&smmu 0x4d0>; pcie_intc: legacy-interrupt-controller { interrupt-controller; -- 2.35.1.1320.gc452695387.dirty ^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets 2026-02-03 0:21 ` [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets Sean Anderson @ 2026-02-04 8:32 ` Pandey, Radhey Shyam 2026-02-05 15:47 ` Sean Anderson 2026-02-10 0:24 ` Rob Herring (Arm) 1 sibling, 1 reply; 6+ messages in thread From: Pandey, Radhey Shyam @ 2026-02-04 8:32 UTC (permalink / raw) To: Sean Anderson, Laurent Pinchart, Vinod Koul, linux-phy@lists.infradead.org Cc: Krzysztof Wilczyński, Lorenzo Pieralisi, linux-kernel@vger.kernel.org, Simek, Michal, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Neil Armstrong, Rob Herring, Havalige, Thippeswamy, Manivannan Sadhasivam, Bjorn Helgaas, Conor Dooley, Krzysztof Kozlowski, devicetree@vger.kernel.org [AMD Official Use Only - AMD Internal Distribution Only] > -----Original Message----- > From: Sean Anderson <sean.anderson@linux.dev> > Sent: Tuesday, February 3, 2026 5:51 AM > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>; Vinod Koul > <vkoul@kernel.org>; linux-phy@lists.infradead.org > Cc: Krzysztof Wilczyński <kwilczynski@kernel.org>; Lorenzo Pieralisi > <lpieralisi@kernel.org>; Pandey, Radhey Shyam > <radhey.shyam.pandey@amd.com>; linux-kernel@vger.kernel.org; Simek, Michal > <michal.simek@amd.com>; linux-arm-kernel@lists.infradead.org; linux- > pci@vger.kernel.org; Neil Armstrong <neil.armstrong@linaro.org>; Rob Herring > <robh@kernel.org>; Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; > Manivannan Sadhasivam <mani@kernel.org>; Bjorn Helgaas > <bhelgaas@google.com>; Sean Anderson <sean.anderson@linux.dev>; Conor > Dooley <conor+dt@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; > devicetree@vger.kernel.org > Subject: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets > > Add resets so we can hold the bridge in reset while we perform phy calibration. Seems like this should a required property? Rest looks fine to me. > > Signed-off-by: Sean Anderson <sean.anderson@linux.dev> > --- > > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > index 9de3c09efb6e..7efb3dd9955f 100644 > --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > @@ -69,6 +69,18 @@ properties: > power-domains: > maxItems: 1 > > + resets: > + maxItems: 3 > + > + reset-names: > + items: > + - description: APB register block reset > + const: cfg > + - description: AXI-PCIe bridge reset > + const: bridge > + - description: PCIe MAC reset > + const: ctrl > + > iommus: > maxItems: 1 > > @@ -117,6 +129,7 @@ examples: > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/power/xlnx-zynqmp-power.h> > + #include <dt-bindings/reset/xlnx-zynqmp-resets.h> > soc { > #address-cells = <2>; > #size-cells = <2>; > @@ -146,6 +159,10 @@ examples: > msi-parent = <&nwl_pcie>; > phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; > power-domains = <&zynqmp_firmware PD_PCIE>; > + resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>, > + <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>, > + <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>; > + reset-names = "cfg", "bridge", "ctrl"; > iommus = <&smmu 0x4d0>; > pcie_intc: legacy-interrupt-controller { > interrupt-controller; > -- > 2.35.1.1320.gc452695387.dirty ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets 2026-02-04 8:32 ` Pandey, Radhey Shyam @ 2026-02-05 15:47 ` Sean Anderson 2026-02-18 16:36 ` Manivannan Sadhasivam 0 siblings, 1 reply; 6+ messages in thread From: Sean Anderson @ 2026-02-05 15:47 UTC (permalink / raw) To: Pandey, Radhey Shyam, Laurent Pinchart, Vinod Koul, linux-phy@lists.infradead.org Cc: Krzysztof Wilczyński, Lorenzo Pieralisi, linux-kernel@vger.kernel.org, Simek, Michal, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Neil Armstrong, Rob Herring, Havalige, Thippeswamy, Manivannan Sadhasivam, Bjorn Helgaas, Conor Dooley, Krzysztof Kozlowski, devicetree@vger.kernel.org On 2/4/26 03:32, Pandey, Radhey Shyam wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > >> -----Original Message----- >> From: Sean Anderson <sean.anderson@linux.dev> >> Sent: Tuesday, February 3, 2026 5:51 AM >> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>; Vinod Koul >> <vkoul@kernel.org>; linux-phy@lists.infradead.org >> Cc: Krzysztof Wilczyński <kwilczynski@kernel.org>; Lorenzo Pieralisi >> <lpieralisi@kernel.org>; Pandey, Radhey Shyam >> <radhey.shyam.pandey@amd.com>; linux-kernel@vger.kernel.org; Simek, Michal >> <michal.simek@amd.com>; linux-arm-kernel@lists.infradead.org; linux- >> pci@vger.kernel.org; Neil Armstrong <neil.armstrong@linaro.org>; Rob Herring >> <robh@kernel.org>; Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; >> Manivannan Sadhasivam <mani@kernel.org>; Bjorn Helgaas >> <bhelgaas@google.com>; Sean Anderson <sean.anderson@linux.dev>; Conor >> Dooley <conor+dt@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; >> devicetree@vger.kernel.org >> Subject: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets >> >> Add resets so we can hold the bridge in reset while we perform phy calibration. > > Seems like this should a required property? It's optional as it does not exist in previous versions of the devicetree. In the past I have received pushback against making these sort of properties required. If the resets don't exist we just don't assert them and assume the bootloader has deasserted them. --Sean > Rest looks fine to me. > >> >> Signed-off-by: Sean Anderson <sean.anderson@linux.dev> >> --- >> >> .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 17 +++++++++++++++++ >> 1 file changed, 17 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> index 9de3c09efb6e..7efb3dd9955f 100644 >> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> @@ -69,6 +69,18 @@ properties: >> power-domains: >> maxItems: 1 >> >> + resets: >> + maxItems: 3 >> + >> + reset-names: >> + items: >> + - description: APB register block reset >> + const: cfg >> + - description: AXI-PCIe bridge reset >> + const: bridge >> + - description: PCIe MAC reset >> + const: ctrl >> + >> iommus: >> maxItems: 1 >> >> @@ -117,6 +129,7 @@ examples: >> #include <dt-bindings/interrupt-controller/irq.h> >> #include <dt-bindings/phy/phy.h> >> #include <dt-bindings/power/xlnx-zynqmp-power.h> >> + #include <dt-bindings/reset/xlnx-zynqmp-resets.h> >> soc { >> #address-cells = <2>; >> #size-cells = <2>; >> @@ -146,6 +159,10 @@ examples: >> msi-parent = <&nwl_pcie>; >> phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; >> power-domains = <&zynqmp_firmware PD_PCIE>; >> + resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>, >> + <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>, >> + <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>; >> + reset-names = "cfg", "bridge", "ctrl"; >> iommus = <&smmu 0x4d0>; >> pcie_intc: legacy-interrupt-controller { >> interrupt-controller; >> -- >> 2.35.1.1320.gc452695387.dirty > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets 2026-02-05 15:47 ` Sean Anderson @ 2026-02-18 16:36 ` Manivannan Sadhasivam 0 siblings, 0 replies; 6+ messages in thread From: Manivannan Sadhasivam @ 2026-02-18 16:36 UTC (permalink / raw) To: Sean Anderson Cc: Pandey, Radhey Shyam, Laurent Pinchart, Vinod Koul, linux-phy@lists.infradead.org, Krzysztof Wilczyński, Lorenzo Pieralisi, linux-kernel@vger.kernel.org, Simek, Michal, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Neil Armstrong, Rob Herring, Havalige, Thippeswamy, Bjorn Helgaas, Conor Dooley, Krzysztof Kozlowski, devicetree@vger.kernel.org On Thu, Feb 05, 2026 at 10:47:21AM -0500, Sean Anderson wrote: > On 2/4/26 03:32, Pandey, Radhey Shyam wrote: > > [AMD Official Use Only - AMD Internal Distribution Only] > > > >> -----Original Message----- > >> From: Sean Anderson <sean.anderson@linux.dev> > >> Sent: Tuesday, February 3, 2026 5:51 AM > >> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>; Vinod Koul > >> <vkoul@kernel.org>; linux-phy@lists.infradead.org > >> Cc: Krzysztof Wilczyński <kwilczynski@kernel.org>; Lorenzo Pieralisi > >> <lpieralisi@kernel.org>; Pandey, Radhey Shyam > >> <radhey.shyam.pandey@amd.com>; linux-kernel@vger.kernel.org; Simek, Michal > >> <michal.simek@amd.com>; linux-arm-kernel@lists.infradead.org; linux- > >> pci@vger.kernel.org; Neil Armstrong <neil.armstrong@linaro.org>; Rob Herring > >> <robh@kernel.org>; Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; > >> Manivannan Sadhasivam <mani@kernel.org>; Bjorn Helgaas > >> <bhelgaas@google.com>; Sean Anderson <sean.anderson@linux.dev>; Conor > >> Dooley <conor+dt@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; > >> devicetree@vger.kernel.org > >> Subject: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets > >> > >> Add resets so we can hold the bridge in reset while we perform phy calibration. > > > > Seems like this should a required property? > > It's optional as it does not exist in previous versions of the > devicetree. In the past I have received pushback against making these > sort of properties required. > > If the resets don't exist we just don't assert them and assume the > bootloader has deasserted them. > If the resets are pretty much required for the hardware functionality, we can mark them as required in the binding and accept the ABI breakage. This scenario keeps coming with devicetree as the initial devicetree bindings lacked full hardware description in most of the cases. - Mani > --Sean > > > Rest looks fine to me. > > > >> > >> Signed-off-by: Sean Anderson <sean.anderson@linux.dev> > >> --- > >> > >> .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 17 +++++++++++++++++ > >> 1 file changed, 17 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > >> b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > >> index 9de3c09efb6e..7efb3dd9955f 100644 > >> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > >> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > >> @@ -69,6 +69,18 @@ properties: > >> power-domains: > >> maxItems: 1 > >> > >> + resets: > >> + maxItems: 3 > >> + > >> + reset-names: > >> + items: > >> + - description: APB register block reset > >> + const: cfg > >> + - description: AXI-PCIe bridge reset > >> + const: bridge > >> + - description: PCIe MAC reset > >> + const: ctrl > >> + > >> iommus: > >> maxItems: 1 > >> > >> @@ -117,6 +129,7 @@ examples: > >> #include <dt-bindings/interrupt-controller/irq.h> > >> #include <dt-bindings/phy/phy.h> > >> #include <dt-bindings/power/xlnx-zynqmp-power.h> > >> + #include <dt-bindings/reset/xlnx-zynqmp-resets.h> > >> soc { > >> #address-cells = <2>; > >> #size-cells = <2>; > >> @@ -146,6 +159,10 @@ examples: > >> msi-parent = <&nwl_pcie>; > >> phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; > >> power-domains = <&zynqmp_firmware PD_PCIE>; > >> + resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>, > >> + <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>, > >> + <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>; > >> + reset-names = "cfg", "bridge", "ctrl"; > >> iommus = <&smmu 0x4d0>; > >> pcie_intc: legacy-interrupt-controller { > >> interrupt-controller; > >> -- > >> 2.35.1.1320.gc452695387.dirty > > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets 2026-02-03 0:21 ` [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets Sean Anderson 2026-02-04 8:32 ` Pandey, Radhey Shyam @ 2026-02-10 0:24 ` Rob Herring (Arm) 1 sibling, 0 replies; 6+ messages in thread From: Rob Herring (Arm) @ 2026-02-10 0:24 UTC (permalink / raw) To: Sean Anderson Cc: Thippeswamy Havalige, Lorenzo Pieralisi, Michal Simek, Krzysztof Wilczyński, Laurent Pinchart, linux-phy, Vinod Koul, Neil Armstrong, Conor Dooley, devicetree, linux-pci, Bjorn Helgaas, Krzysztof Kozlowski, Radhey Shyam Pandey, Manivannan Sadhasivam, linux-arm-kernel, linux-kernel On Mon, 02 Feb 2026 19:21:21 -0500, Sean Anderson wrote: > Add resets so we can hold the bridge in reset while we perform phy > calibration. > > Signed-off-by: Sean Anderson <sean.anderson@linux.dev> > --- > > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-02-18 16:36 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-02-03 0:21 [PATCH 0/8] phy: zynqmp: Perform complete initialization, including ILL calibration Sean Anderson 2026-02-03 0:21 ` [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets Sean Anderson 2026-02-04 8:32 ` Pandey, Radhey Shyam 2026-02-05 15:47 ` Sean Anderson 2026-02-18 16:36 ` Manivannan Sadhasivam 2026-02-10 0:24 ` Rob Herring (Arm)
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