Re: [PATCH v3 2/2] dt-binding: riscv: Clarify the riscv,ndev meaning in PLIC

[Conor Dooley <conor@kernel.org>]

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On Wed, Feb 04, 2026 at 01:21:48AM +0800, Yangyu Chen wrote:
> In PLIC, interrupt source 0 is reserved and should not be used.
> Therefore, the valid interrupt sources are from 1 to riscv,ndev
> inclusive. This commit updates the documentation to clarify this point.
> 
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 388fc2c620c0..df9578bcac89 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -109,6 +109,8 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description:
>        Specifies how many external interrupts are supported by this controller.
> +      Note that source 0 is reserved in PLIC, so the valid interrupt sources
> +      are 1 to riscv,ndev inclusive.

The trm for mpfs says "in the plic, global interrupt id 0 means 'no
interrupt'". That sounds subtly different to me than "reserved", but
/shrug
I think this could just be truncated to "Valid interrupt sources are
1 to riscv,ndev, inclusive.".
Acked-by: Conor Dooley <conor.dooley@microchip.com>

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