From: Conor Dooley <conor@kernel.org>
To: Lv Zheng <lv.zheng@linux.spacemit.com>
Cc: Tomasz Jeznach <tjeznach@rivosinc.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Jingyu Li <joey.li@spacemit.com>,
Zhijian Chen <zhijian@spacemit.com>,
iommu@lists.linux.dev, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 4/8] dt-bindings: iommu: Add spacemit/t100 features
Date: Wed, 4 Feb 2026 17:37:08 +0000 [thread overview]
Message-ID: <20260204-primer-wrought-6f64b14bf152@spud> (raw)
In-Reply-To: <A0E91F323138E92F+a27d73b00f3324f0d3885128f5596230b3f1370b.1770195980.git.lv.zheng@linux.spacemit.com>
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On Wed, Feb 04, 2026 at 05:09:12PM +0800, Lv Zheng wrote:
> Adds device tree bindings for SpacemiT T100 specific features by
> introducing spacemit,100 compatible. T100 contains distributed IOATCs,
> each of which exposes pmiv interrupt.
>
> Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
> Signed-off-by: Jingyu Li <joey.li@spacemit.com>
> ---
> .../bindings/iommu/riscv,iommu.yaml | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> index d4838c3b3741..2da3456e7402 100644
> --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> @@ -32,6 +32,12 @@ properties:
> # should be specified along with 'reg' property providing MMIO location.
> compatible:
> oneOf:
> + - description: SpacemiT distributed IOMMUs
> + items:
> + - enum:
> + - spacemit,t100
> + - const: spacemit,riscv-iommu
What actually is the t100? Is it an SoC or is it the name of the core
complex IP that spacemit is using in multiple SoCs?
> + - const: riscv,iommu
> - items:
> - enum:
> - qemu,riscv-iommu
> @@ -75,6 +81,23 @@ required:
>
> additionalProperties: false
>
> +select: false
Why is this here? It just breaks the whole binding.
pw-bot: changes-requested
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: spacemit,riscv-iommu
> + then:
> + properties:
> + interrupts:
> + maxItems: 68
This isn't right. You would need to make the interrupts property itself
have maxItems: 68, then add an else to this conditional that has
maxItems: 4. What you've done just doesn't work, and if you removed the
"select: false: you'd see.
> + description:
> + SpacemiT distributed IOMMU includes additional interrupts for
> + IOATCs. Each IOATC exposes pmiv wired vector as standalone
> + interrupt and the maximum number of IOATCs can be up to 64.
> +
> examples:
> - |+
> /* Example 1 (IOMMU device with wired interrupts) */
> @@ -145,3 +168,17 @@ examples:
> };
> };
> };
> +
> + - |+
> + /* Example 5 (SpacemiT distributed IOMMU) */
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + iommu4: iommu@1bccd000 {
Remove the iommu4 label, there's no references to it.
Cheers,
Conor.
> + compatible = "spacemit,t100", "spacemit,riscv-iommu", "riscv,iommu";
> + reg = <0x1bccd000 0x1000>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>, <58 IRQ_TYPE_LEVEL_HIGH>,
> + <58 IRQ_TYPE_LEVEL_HIGH>, <58 IRQ_TYPE_LEVEL_HIGH>,
> + <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&saplic>;
> + #iommu-cells = <0x01>;
> + };
> --
> 2.43.0
>
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next prev parent reply other threads:[~2026-02-04 17:37 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1769562575.git.lv.zheng@spacemit.com>
2026-01-29 6:08 ` [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-01-29 6:08 ` [PATCH v1.1 1/7] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-01-29 6:08 ` [PATCH v1.1 2/7] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-01-29 6:08 ` [PATCH v1.1 3/7] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-01-29 6:09 ` [PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-01-29 10:08 ` Conor Dooley
2026-01-29 10:43 ` 郑律
2026-01-29 16:41 ` Conor Dooley
2026-01-29 17:06 ` Robin Murphy
2026-01-30 1:30 ` 郑律
2026-01-30 1:39 ` 郑律
2026-01-29 6:09 ` [PATCH v1.1 5/7] spacemit/t100: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-01-29 6:09 ` [PATCH v1.1 6/7] spacemit/t100: Add global filter " Lv Zheng
2026-01-29 6:09 ` [PATCH v1.1 7/7] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-06 10:44 ` [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Krzysztof Kozlowski
2026-02-04 9:08 ` [PATCH v3 0/8] " Lv Zheng
2026-02-06 10:44 ` Krzysztof Kozlowski
2026-02-07 3:41 ` Lv Zheng
2026-02-13 22:21 ` Yixun Lan
2026-02-27 5:55 ` Lv Zheng
[not found] ` <cover.1770195980.git.lv.zheng@linux.spacemit.com>
2026-02-04 9:08 ` [PATCH v3 1/8] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-02-04 9:08 ` [PATCH v3 2/8] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-02-04 17:20 ` Andrew Jones
2026-02-05 3:52 ` Lv Zheng
2026-02-05 15:04 ` Andrew Jones
2026-02-06 1:36 ` Lv Zheng
2026-02-04 9:09 ` [PATCH v3 3/8] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-02-04 18:39 ` Andrew Jones
2026-02-05 2:11 ` Zong Li
2026-02-05 3:35 ` Lv Zheng
2026-02-05 3:47 ` Zong Li
2026-02-05 6:11 ` Lv Zheng
2026-02-05 15:23 ` Andrew Jones
2026-02-06 3:42 ` Lv Zheng
2026-02-06 15:09 ` Andrew Jones
2026-02-07 2:11 ` Zong Li
2026-02-04 9:09 ` [PATCH v3 4/8] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-02-04 17:37 ` Conor Dooley [this message]
2026-02-05 3:11 ` Lv Zheng
2026-02-05 18:24 ` Conor Dooley
2026-02-06 1:33 ` Lv Zheng
2026-02-06 10:24 ` Conor Dooley
2026-02-07 4:24 ` Lv Zheng
2026-02-07 14:55 ` Conor Dooley
2026-02-04 9:09 ` [PATCH v3 5/8] riscv/iommu: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-02-04 9:09 ` [PATCH v3 6/8] spacemit/t100: Add global filter awareness " Lv Zheng
2026-02-04 9:09 ` [PATCH v3 7/8] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-04 9:09 ` [PATCH v3 8/8] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing Lv Zheng
2026-02-04 17:38 ` Conor Dooley
2026-02-05 3:22 ` Lv Zheng
2026-02-05 9:09 ` [PATCH v4 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-02-06 10:46 ` Krzysztof Kozlowski
2026-02-07 3:54 ` Lv Zheng
[not found] ` <cover.1770281596.git.lv.zheng@linux.spacemit.com>
2026-02-05 9:10 ` [PATCH v4 1/7] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-02-05 9:10 ` [PATCH v4 2/7] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-02-05 9:10 ` [PATCH v4 3/7] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-02-05 18:26 ` Conor Dooley
2026-02-06 3:44 ` Lv Zheng
2026-02-05 9:10 ` [PATCH v4 4/7] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-02-05 9:11 ` [PATCH v4 5/7] spacemit/t100: Add global filter awareness " Lv Zheng
2026-02-05 9:11 ` [PATCH v4 6/7] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-05 9:11 ` [PATCH v4 7/7] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing Lv Zheng
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