[PATCH 0/3] SDM670 cache controller support

[PATCH 0/3] SDM670 cache controller support

[Richard Acayan]

This adds support for the Low-Level Cache Controller (LLCC) on SDM670.

Richard Acayan (3):
  dt-bindings: cache: qcom,llcc: Add SDM670 compatible
  soc: qcom: llcc: Add configuration data for SDM670
  arm64: dts: qcom: sdm670: add llcc

 .../devicetree/bindings/cache/qcom,llcc.yaml  |   2 +
 arch/arm64/boot/dts/qcom/sdm670.dtsi          |  11 ++
 drivers/soc/qcom/llcc-qcom.c                  | 105 ++++++++++++++++++
 3 files changed, 118 insertions(+)

-- 
2.53.0

[PATCH 1/3] dt-bindings: cache: qcom,llcc: Add SDM670 compatible

[Richard Acayan]

Document the Last Level Cache Controller on SDM670.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
 Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index a620a2ff5c56..0de39b7b3f48 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -32,6 +32,7 @@ properties:
       - qcom,sc7280-llcc
       - qcom,sc8180x-llcc
       - qcom,sc8280xp-llcc
+      - qcom,sdm670-llcc
       - qcom,sdm845-llcc
       - qcom,sm6350-llcc
       - qcom,sm7150-llcc
@@ -162,6 +163,7 @@ allOf:
           contains:
             enum:
               - qcom,sc7280-llcc
+              - qcom,sdm670-llcc
     then:
       properties:
         reg:
-- 
2.53.0

[PATCH 2/3] soc: qcom: llcc: Add configuration data for SDM670

[Richard Acayan]

Add system cache table and configs for the SDM670 SoC.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
 drivers/soc/qcom/llcc-qcom.c | 105 +++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 13e174267294..c5f7647ec8de 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -1591,6 +1591,94 @@ static const struct llcc_slice_config sc8280xp_data[] = {
 	},
 };
 
+static const struct llcc_slice_config sdm670_data[] = {
+	{
+		.usecase_id = LLCC_CPUSS,
+		.slice_id = 1,
+		.max_cap = 512,
+		.priority = 1,
+		.bonus_ways = 0xf,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_ROTATOR,
+		.slice_id = 4,
+		.max_cap = 384,
+		.priority = 2,
+		.fixed_size = true,
+		.bonus_ways = 0x0,
+		.res_ways = 0xe,
+		.cache_mode = 2,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+	}, {
+		.usecase_id = LLCC_VOICE,
+		.slice_id = 5,
+		.max_cap = 512,
+		.priority = 1,
+		.bonus_ways = 0xf,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+	}, {
+		.usecase_id = LLCC_AUDIO,
+		.slice_id = 6,
+		.max_cap = 512,
+		.priority = 1,
+		.bonus_ways = 0xf,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+	}, {
+		.usecase_id = LLCC_MDM,
+		.slice_id = 8,
+		.max_cap = 512,
+		.priority = 1,
+		.bonus_ways = 0xf,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+	}, {
+		.usecase_id = LLCC_GPU,
+		.slice_id = 12,
+		.max_cap = 384,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0x0,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+	}, {
+		.usecase_id = LLCC_MMUHWT,
+		.slice_id = 13,
+		.max_cap = 512,
+		.priority = 1,
+		.bonus_ways = 0xf,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.activate_on_init = true,
+	}, {
+		.usecase_id = LLCC_AUDHW,
+		.slice_id = 22,
+		.max_cap = 512,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xf,
+		.res_ways = 0x0,
+		.cache_mode = 0,
+		.dis_cap_alloc = true,
+		.retain_on_pc = true,
+	},
+};
+
 static const struct llcc_slice_config sdm845_data[] =  {{
 		.usecase_id = LLCC_CPUSS,
 		.slice_id = 1,
@@ -3995,6 +4083,17 @@ static const struct qcom_llcc_config sc8280xp_cfg[] = {
 	},
 };
 
+static const struct qcom_llcc_config sdm670_cfg[] = {
+	{
+		.sct_data	= sdm670_data,
+		.size		= ARRAY_SIZE(sdm670_data),
+		.skip_llcc_cfg	= true,
+		.reg_offset	= llcc_v1_reg_offset,
+		.edac_reg_offset = &llcc_v1_edac_reg_offset,
+		.no_edac	= true,
+	},
+};
+
 static const struct qcom_llcc_config sdm845_cfg[] = {
 	{
 		.sct_data	= sdm845_data,
@@ -4158,6 +4257,11 @@ static const struct qcom_sct_config sc8280xp_cfgs = {
 	.num_config	= ARRAY_SIZE(sc8280xp_cfg),
 };
 
+static const struct qcom_sct_config sdm670_cfgs = {
+	.llcc_config	= sdm670_cfg,
+	.num_config	= ARRAY_SIZE(sdm670_cfg),
+};
+
 static const struct qcom_sct_config sdm845_cfgs = {
 	.llcc_config	= sdm845_cfg,
 	.num_config	= ARRAY_SIZE(sdm845_cfg),
@@ -4953,6 +5057,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
 	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
 	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
 	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
+	{ .compatible = "qcom,sdm670-llcc", .data = &sdm670_cfgs },
 	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
 	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
 	{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
-- 
2.53.0

[PATCH 3/3] arm64: dts: qcom: sdm670: add llcc

[Richard Acayan]

Add the Last Level Cache Controller (LLCC) for the SDM670.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index b8a8dcbdfbe3..b5f832ca42f4 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1130,6 +1130,17 @@ refgen: regulator@ff1000 {
 			reg = <0x0 0x00ff1000 0x0 0x60>;
 		};
 
+		llcc: system-cache-controller@1100000 {
+			compatible = "qcom,sdm670-llcc";
+			reg = <0 0x01100000 0 0x50000>,
+			      <0 0x01180000 0 0x50000>,
+			      <0 0x01300000 0 0x50000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc_broadcast_base";
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		mem_noc: interconnect@1380000 {
 			compatible = "qcom,sdm670-mem-noc";
 			reg = <0 0x01380000 0 0x27200>;
-- 
2.53.0

Re: [PATCH 2/3] soc: qcom: llcc: Add configuration data for SDM670

[Konrad Dybcio]

On 2/10/26 3:19 AM, Richard Acayan wrote:
> Add system cache table and configs for the SDM670 SoC.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---

I have a clone of some msm-4.9 on my ssd and it roughly matches this
patch

However

In docs, I see a version with only CPU_SS, MODEM and MMUHWT left
(your settings here seem to match), dated later than the last commit
to llcc-sdm670.c in that downstream kernel clone..

Because this SoC seems to only have 512KiB of LLC in total, it may
be that it was found in testing for that configuration to have a
better perf profile

Could you please give it a shot and check if you see any immediate
gains/losses?

Konrad

Re: [PATCH 1/3] dt-bindings: cache: qcom,llcc: Add SDM670 compatible

[Krzysztof Kozlowski]

On Mon, Feb 09, 2026 at 09:19:55PM -0500, Richard Acayan wrote:
> Document the Last Level Cache Controller on SDM670.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
>  Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: sdm670: add llcc

[Konrad Dybcio]

On 2/10/26 3:19 AM, Richard Acayan wrote:
> Add the Last Level Cache Controller (LLCC) for the SDM670.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 2/3] soc: qcom: llcc: Add configuration data for SDM670

[Konrad Dybcio]

On 2/10/26 3:19 AM, Richard Acayan wrote:
> Add system cache table and configs for the SDM670 SoC.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---

[...]

> +static const struct qcom_llcc_config sdm670_cfg[] = {
> +	{
> +		.sct_data	= sdm670_data,
> +		.size		= ARRAY_SIZE(sdm670_data),
> +		.skip_llcc_cfg	= true,
> +		.reg_offset	= llcc_v1_reg_offset,
> +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> +		.no_edac	= true,

Does the EDAC driver crash the device?

Konrad

Re: [PATCH 2/3] soc: qcom: llcc: Add configuration data for SDM670

[Richard Acayan]

On Tue, Feb 10, 2026 at 10:29:16AM +0100, Konrad Dybcio wrote:
> On 2/10/26 3:19 AM, Richard Acayan wrote:
> > Add system cache table and configs for the SDM670 SoC.
> > 
> > Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> > ---
> 
> [...]
> 
> > +static const struct qcom_llcc_config sdm670_cfg[] = {
> > +	{
> > +		.sct_data	= sdm670_data,
> > +		.size		= ARRAY_SIZE(sdm670_data),
> > +		.skip_llcc_cfg	= true,
> > +		.reg_offset	= llcc_v1_reg_offset,
> > +		.edac_reg_offset = &llcc_v1_edac_reg_offset,
> > +		.no_edac	= true,
> 
> Does the EDAC driver crash the device?

Yes, this is needed if the EDAC driver is an available module.

Re: [PATCH 2/3] soc: qcom: llcc: Add configuration data for SDM670

[Richard Acayan]

On Tue, Feb 10, 2026 at 10:27:40AM +0100, Konrad Dybcio wrote:
> On 2/10/26 3:19 AM, Richard Acayan wrote:
> > Add system cache table and configs for the SDM670 SoC.
> > 
> > Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> > ---
> 
> I have a clone of some msm-4.9 on my ssd and it roughly matches this
> patch
> 
> However
> 
> In docs, I see a version with only CPU_SS, MODEM and MMUHWT left
> (your settings here seem to match), dated later than the last commit
> to llcc-sdm670.c in that downstream kernel clone..
> 
> Because this SoC seems to only have 512KiB of LLC in total, it may
> be that it was found in testing for that configuration to have a
> better perf profile
> 
> Could you please give it a shot and check if you see any immediate
> gains/losses?

I don't notice a difference outside the margin of error. The Unixbench
workload reported 4550.4 with all configs, and 4550.9 with only
LLCC_CPUSS, LLCC_MDM, and LLCC_MMUHWT. My 15-second workload on
Hexagon/CDSP was half a second faster when commenting out the cache use
cases.

I don't see better startup times either.

Re: [PATCH 2/3] soc: qcom: llcc: Add configuration data for SDM670

[Konrad Dybcio]

On 2/11/26 8:21 PM, Richard Acayan wrote:
> On Tue, Feb 10, 2026 at 10:27:40AM +0100, Konrad Dybcio wrote:
>> On 2/10/26 3:19 AM, Richard Acayan wrote:
>>> Add system cache table and configs for the SDM670 SoC.
>>>
>>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
>>> ---
>>
>> I have a clone of some msm-4.9 on my ssd and it roughly matches this
>> patch
>>
>> However
>>
>> In docs, I see a version with only CPU_SS, MODEM and MMUHWT left
>> (your settings here seem to match), dated later than the last commit
>> to llcc-sdm670.c in that downstream kernel clone..
>>
>> Because this SoC seems to only have 512KiB of LLC in total, it may
>> be that it was found in testing for that configuration to have a
>> better perf profile
>>
>> Could you please give it a shot and check if you see any immediate
>> gains/losses?
> 
> I don't notice a difference outside the margin of error. The Unixbench
> workload reported 4550.4 with all configs, and 4550.9 with only
> LLCC_CPUSS, LLCC_MDM, and LLCC_MMUHWT. My 15-second workload on
> Hexagon/CDSP was half a second faster when commenting out the cache use
> cases.
> 
> I don't see better startup times either.

Okay, let's stick with the one you posted then. I (briefly) skimmed
through it and seems to be in line with that aforementioned downstream
tree

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: (subset) [PATCH 0/3] SDM670 cache controller support

[Bjorn Andersson]

On Mon, 09 Feb 2026 21:19:54 -0500, Richard Acayan wrote:
> This adds support for the Low-Level Cache Controller (LLCC) on SDM670.
> 
> Richard Acayan (3):
>   dt-bindings: cache: qcom,llcc: Add SDM670 compatible
>   soc: qcom: llcc: Add configuration data for SDM670
>   arm64: dts: qcom: sdm670: add llcc
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: cache: qcom,llcc: Add SDM670 compatible
      commit: 12cf1b5de820bc302f92221d87ae13ec1c760c84
[2/3] soc: qcom: llcc: Add configuration data for SDM670
      commit: 11080cc4af8f0ee4b88d0e51384765bb78f05bf5

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>