* [PATCH v2 1/9] dt-bindings: bus: document the RISAB firewall peripheral
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-13 15:07 ` Krzysztof Kozlowski
2026-02-12 10:10 ` [PATCH v2 2/9] bus: add RISAB dump debug driver Gatien Chevallier
` (7 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
Add documentation on the Resource ISolation peripheral unit for
Address space protection (Block-based) (RISAB) peripheral that is a
memory firewall on the stm32mp2x platforms protecting internal RAMs.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
.../bindings/bus/st,stm32mp25-risab.yaml | 75 ++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-risab.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-risab.yaml
new file mode 100644
index 000000000000..f614f2287751
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-risab.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32mp25-risab.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Resource ISolation peripheral unit for Address space protection
+ (Block-based) (RISAB)
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+description:
+ The Resource Isolation Framework (RIF) is a comprehensive set of hardware
+ blocks designed to enforce and manage isolation of STM32 hardware resources,
+ like memory and peripherals. The RISAB peripheral is part of the RIF and is
+ used to protect internal RAMs by applying access rights per RISAB fixed-size
+ page. Through RISAB registers, a trusted domain, or the domain to whom the
+ page configuration has been delegated, assigns memory pages to one or more
+ security domains (secure, privilege, compartment).
+
+properties:
+ compatible:
+ const: st,stm32mp25-risab
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RISAB bus clock
+
+ memory-region:
+ minItems: 1
+ maxItems: 32
+ description:
+ Phandle to nodes describing memory regions to be configured in the RISAB
+ by the trusted domain of at least a RISAB page size.
+ These regions cannot overlap. A region must be within st,mem-map range and
+ can be represented by one or more pages. RISAB has a 4kBytes page
+ granularity and each page can hold different access rights.
+
+ st,mem-map:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Memory address range covered by the RISAB.
+ items:
+ - description: Memory range base address
+ - description: Memory range size
+
+ st,srwiad:
+ description:
+ When set, the trusted domain configures the RISAB to allow secure
+ read/write data accesses to non-secure blocks and pages. Secure execute
+ remains illegal.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - st,mem-map
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+
+ firewall@420f0000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x420f0000 0x1000>;
+ clocks = <&rcc CK_ICN_LS_MCU>;
+ st,mem-map = <0xa000000 0x20000>;
+ st,srwiad;
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/9] dt-bindings: bus: document the RISAB firewall peripheral
2026-02-12 10:10 ` [PATCH v2 1/9] dt-bindings: bus: document the RISAB firewall peripheral Gatien Chevallier
@ 2026-02-13 15:07 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-02-13 15:07 UTC (permalink / raw)
To: Gatien Chevallier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Michael Turquette,
Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk
On 12/02/2026 11:10, Gatien Chevallier wrote:
> +
> + memory-region:
> + minItems: 1
> + maxItems: 32
> + description:
> + Phandle to nodes describing memory regions to be configured in the RISAB
> + by the trusted domain of at least a RISAB page size.
> + These regions cannot overlap. A region must be within st,mem-map range and
> + can be represented by one or more pages. RISAB has a 4kBytes page
> + granularity and each page can hold different access rights.
> +
> + st,mem-map:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Memory address range covered by the RISAB.
> + items:
> + - description: Memory range base address
> + - description: Memory range size
I did reply at v1 now. This is not a trivial device so should not be rushed.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/9] bus: add RISAB dump debug driver
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 1/9] dt-bindings: bus: document the RISAB firewall peripheral Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 3/9] bus: rifsc: use new CONFIG_STM32_FIREWALL_DEBUG switch Gatien Chevallier
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier, Theo GOUREAU
The Resource ISolation peripheral unit for Address space protection
(Block-based)(RISAB) is a memory firewall peripheral protecting
internal RAMs and is part of the STM32 Resource Isolation Framework
(RIF).
RIF configuration on stm32mp2x platforms can be quite complex.
Especially for memory firewalls. The RISAB configuration is done by
the Trusted Domain that is running in secure privileged mode.
However, its configuration can be read in any mode.
In order to facilitate the memory firewall configuration (check if
correctly applied, what rights for which range, etc...), add a RISAB
configuration dump driver that creates a debugfs entry as an
interactive way of looking at RISAB configuration.
This debugfs entry is a heavy printing function when read so be aware
that reading it will involve significant time in the driver.
Introduce CONFIG_STM32_FIREWALL_DEBUG configuration switch to
enable STM32 firewall drivers configuration dump.
Co-developed-by: Theo GOUREAU <theo.goureau-ext@st.com>
Signed-off-by: Theo GOUREAU <theo.goureau-ext@st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
drivers/bus/Kconfig | 9 ++
drivers/bus/Makefile | 1 +
drivers/bus/stm32_risab.c | 336 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 346 insertions(+)
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index fe7600283e70..1b12de2854ab 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -179,6 +179,15 @@ config STM32_FIREWALL
hardware resources linked to a firewall controller can be requested
through this STM32 framework.
+config STM32_FIREWALL_DEBUG
+ tristate "STM32 Firewall drivers debug features"
+ depends on STM32_FIREWALL && DEBUG_FS
+ help
+ Say y to enable STM32 firewall configuration debug features. This
+ will cause the generation of a "stm32_firewall" directory in the
+ debugfs with entries for each firewall driver capable of dumping
+ its configuration.
+
config SUN50I_DE2_BUS
bool "Allwinner A64 DE2 Bus Driver"
default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 8e693fe8a03a..a0447682c314 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o stm32_etzpc.o
+obj-$(CONFIG_STM32_FIREWALL_DEBUG) += stm32_risab.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_OF) += simple-pm-bus.o
diff --git a/drivers/bus/stm32_risab.c b/drivers/bus/stm32_risab.c
new file mode 100644
index 000000000000..794c2bf40a2d
--- /dev/null
+++ b/drivers/bus/stm32_risab.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/*
+ * RISAB constants
+ */
+#define RISAB_NUMBER_OF_PAGES_MAX 32
+#define RISAB_BLOCKS_PER_PAGES 8
+#define RISAB_NUMBER_OF_CID 7
+#define RISAB_PAGE_SIZE 0x1000
+
+/*
+ * RISAB configuration register
+ */
+#define RISAB_CR 0x000
+#define RISAB_CR_SRWIAD BIT(31)
+#define RISAB_CR_GLOCK BIT(0)
+
+/*
+ * RISAB configuration lock register
+ */
+#define RISAB_RCFGLOCKR 0x010
+
+/*
+ * RISAB page y=0..31 security and privileged configuration registers
+ */
+#define RISAB_PG_SECCFGR(y) (0x100 + 0x4 * (y))
+#define RISAB_PG_PRIVCFGR(y) (0x200 + 0x4 * (y))
+#define RISAB_PG_C2PRIVCFGR(y) (0x600 + 0x4 * (y))
+
+/*
+ * RISAB compartment x=0..6 privilege, read and write configuration registers
+ */
+#define RISAB_CIDPRIVCFGR(x) (0x800 + 0x20 * (x))
+#define RISAB_CIDRDCFGR(x) (0x808 + 0x20 * (x))
+#define RISAB_CIDWRCFGR(x) (0x810 + 0x20 * (x))
+
+/*
+ * RISAB page y=0..31 CID configuration registers
+ */
+#define RISAB_PG_CIDCFGR(y) (0xA00 + 0x4 * (y))
+#define RISAB_PG_CIDCFGR_DCCID_MASK GENMASK(6, 4)
+#define RISAB_PG_CIDCFGR_DCEN BIT(2)
+#define RISAB_PG_CIDCFGR_CFEN BIT(0)
+
+/*
+ * RISAB hardware configuration registers
+ */
+#define RISAB_HWCFGR1 0xFF0
+#define RISAB_HWCFGR1_LOG_NUM_PAGE_MASK GENMASK(27, 24)
+#define RISAB_HWCFGR1_LOG_NUM_PAGE_SHIFT 24
+
+struct risab_debug_data {
+ bool sec[RISAB_BLOCKS_PER_PAGES];
+ bool priv[RISAB_BLOCKS_PER_PAGES];
+ bool c2priv[RISAB_BLOCKS_PER_PAGES];
+ u8 dccid;
+ bool dcen;
+ bool cfen;
+};
+
+struct risab_generic_debug_data {
+ bool srwiad;
+ bool glock;
+ bool rlock[RISAB_NUMBER_OF_PAGES_MAX];
+ bool ppriv[RISAB_NUMBER_OF_CID][RISAB_NUMBER_OF_PAGES_MAX];
+ bool prden[RISAB_NUMBER_OF_CID][RISAB_NUMBER_OF_PAGES_MAX];
+ bool pwren[RISAB_NUMBER_OF_CID][RISAB_NUMBER_OF_PAGES_MAX];
+};
+
+struct risab_pdata {
+ void __iomem *base;
+ struct clk *clk;
+ struct device *dev;
+ struct dentry *dbg_entry;
+ u32 phys_base;
+ u32 risab_map_base;
+ u32 nb_pages;
+};
+
+static void stm32_risab_fill_dev_dbg_entry(struct risab_pdata *pdata,
+ struct risab_debug_data *dbg_entry, int page)
+{
+ u32 risab_pg_c2privcfgr = readl_relaxed(pdata->base + RISAB_PG_C2PRIVCFGR(page));
+ u32 risab_pg_privcfgr = readl_relaxed(pdata->base + RISAB_PG_PRIVCFGR(page));
+ u32 risab_pg_seccfgr = readl_relaxed(pdata->base + RISAB_PG_SECCFGR(page));
+ u32 risab_pg_cidcfgr = readl_relaxed(pdata->base + RISAB_PG_CIDCFGR(page));
+ int block;
+
+ for (block = 0; block < RISAB_BLOCKS_PER_PAGES; block++) {
+ dbg_entry->sec[block] = risab_pg_seccfgr & BIT(block);
+ dbg_entry->priv[block] = risab_pg_privcfgr & BIT(block);
+ dbg_entry->c2priv[block] = risab_pg_c2privcfgr & BIT(block);
+ }
+
+ dbg_entry->dccid = FIELD_GET(RISAB_PG_CIDCFGR_DCCID_MASK, risab_pg_cidcfgr);
+ dbg_entry->dcen = risab_pg_cidcfgr & RISAB_PG_CIDCFGR_DCEN;
+ dbg_entry->cfen = risab_pg_cidcfgr & RISAB_PG_CIDCFGR_CFEN;
+}
+
+static void stm32_risab_fill_dev_generic_dbg_entry(struct risab_pdata *pdata,
+ struct risab_generic_debug_data *dbg_entry)
+{
+ u32 risab_rcfglockr = readl_relaxed(pdata->base + RISAB_RCFGLOCKR);
+ u32 risab_cr = readl_relaxed(pdata->base + RISAB_CR);
+ int page, compartment;
+
+ dbg_entry->srwiad = risab_cr & RISAB_CR_SRWIAD;
+ dbg_entry->glock = risab_cr & RISAB_CR_GLOCK;
+
+ for (page = 0; page < pdata->nb_pages; page++)
+ dbg_entry->rlock[page] = risab_rcfglockr & BIT(page);
+
+ for (compartment = 0; compartment < RISAB_NUMBER_OF_CID; compartment++) {
+ u32 risab_cidprivcfgr = readl_relaxed(pdata->base + RISAB_CIDPRIVCFGR(compartment));
+ u32 risab_cidrdcfgr = readl_relaxed(pdata->base + RISAB_CIDRDCFGR(compartment));
+ u32 risab_cidwrcfgr = readl_relaxed(pdata->base + RISAB_CIDWRCFGR(compartment));
+
+ for (page = 0; page < pdata->nb_pages; page++) {
+ dbg_entry->ppriv[compartment][page] = risab_cidprivcfgr & BIT(page);
+ dbg_entry->prden[compartment][page] = risab_cidrdcfgr & BIT(page);
+ dbg_entry->pwren[compartment][page] = risab_cidwrcfgr & BIT(page);
+ }
+ }
+}
+
+static int stm32_risab_conf_dump_show(struct seq_file *s, void *data)
+{
+ struct risab_pdata *pdata = (struct risab_pdata *)s->private;
+ struct risab_generic_debug_data generic_dbg_entry;
+ struct risab_debug_data dbg_entry;
+ int ret, page, compartment, block;
+
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret) {
+ dev_err(pdata->dev, "Couldn't enable RISAB clock");
+ return ret;
+ }
+
+ stm32_risab_fill_dev_generic_dbg_entry(pdata, &generic_dbg_entry);
+
+ seq_puts(s, "=============================================\n");
+ seq_printf(s, " RISAB dump (%s)\n", pdata->dev->of_node->full_name);
+ seq_puts(s, "=============================================\n");
+
+ seq_printf(s, "Secure read/write illegal access disable (SRWIAD): %d.\n",
+ generic_dbg_entry.srwiad);
+ seq_printf(s, "Global lock (GLOCK): %d.\n", generic_dbg_entry.glock);
+
+ seq_puts(s, "| Page |");
+ seq_puts(s, "| Res. |");
+ seq_puts(s, "| priv. (p) read (r) write (w) per compartment |");
+ seq_puts(s, "| Delegated |");
+ seq_puts(s, "| CID |");
+ seq_puts(s, "| secure (s) default priv. (p) compartment2 priv. (P) per block |\n");
+
+ seq_puts(s, "| start add. end add. |");
+ seq_puts(s, "| lock |");
+ seq_puts(s, "| CID0 | CID1 | CID2 | CID3 | CID4 | CID5 | CID6 |");
+ seq_puts(s, "| conf. CID |");
+ seq_puts(s, "| filtering |");
+ seq_puts(s, "| blck0 | blck1 | blck2 | blck3 | blck4 | blck5 | blck6 | blck7 |\n");
+
+ for (page = 0; page < pdata->nb_pages; page++) {
+ stm32_risab_fill_dev_dbg_entry(pdata, &dbg_entry, page);
+ seq_printf(s, "| %2d 0x%08x 0x%08x |",
+ page,
+ pdata->risab_map_base + page * RISAB_PAGE_SIZE,
+ pdata->risab_map_base + (page + 1) * RISAB_PAGE_SIZE - 1
+ );
+ seq_printf(s, "| %3s |", generic_dbg_entry.rlock[page] ? "Yes" : "No");
+ for (compartment = 0; compartment < RISAB_NUMBER_OF_CID; compartment++) {
+ seq_printf(s, "| %1s %1s %1s ",
+ generic_dbg_entry.ppriv[compartment][page] ? "p" : " ",
+ generic_dbg_entry.prden[compartment][page] ? "r" : " ",
+ generic_dbg_entry.pwren[compartment][page] ? "w" : " "
+ );
+ }
+
+ if (dbg_entry.dcen)
+ seq_printf(s, "|| 0x%04x |", dbg_entry.dccid);
+ else
+ seq_puts(s, "|| disabled |");
+
+ seq_printf(s, "| %-9s |", dbg_entry.cfen ? "enabled" : "disabled");
+ for (block = 0; block < RISAB_BLOCKS_PER_PAGES; block++) {
+ seq_printf(s, "| %1s %1s %1s ",
+ dbg_entry.sec[block] ? "s" : " ",
+ dbg_entry.priv[block] && !dbg_entry.cfen ? "p" : " ",
+ dbg_entry.c2priv[block] ? "P" : " "
+ );
+ }
+ seq_puts(s, "|\n");
+ }
+
+ clk_disable_unprepare(pdata->clk);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(stm32_risab_conf_dump);
+
+static int stm32_risab_register_debugfs(struct risab_pdata *pdata)
+{
+ struct dentry *root = NULL;
+ char risab_name[15];
+
+ root = debugfs_lookup("stm32_firewall", NULL);
+ if (!root)
+ root = debugfs_create_dir("stm32_firewall", NULL);
+
+ if (IS_ERR(root))
+ return PTR_ERR(root);
+
+ scnprintf(risab_name, sizeof(risab_name), "risab@%x", pdata->phys_base);
+
+ pdata->dbg_entry = debugfs_create_file(risab_name, 0444, root, pdata,
+ &stm32_risab_conf_dump_fops);
+
+ return 0;
+}
+
+static int stm32_risab_get_nb_pages(struct risab_pdata *pdata)
+{
+ u32 risab_hwcfgr1, nb_pages_shift;
+ int ret, nb_page;
+
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret) {
+ dev_err(pdata->dev, "Failed to enable clk: %d\n", ret);
+ return ret;
+ }
+
+ risab_hwcfgr1 = readl_relaxed(pdata->base + RISAB_HWCFGR1);
+ nb_pages_shift = FIELD_GET(RISAB_HWCFGR1_LOG_NUM_PAGE_MASK,
+ risab_hwcfgr1);
+ nb_page = BIT(nb_pages_shift);
+
+ if (nb_page > RISAB_NUMBER_OF_PAGES_MAX) {
+ dev_err(pdata->dev, "RISAB number of pages is greater than %d",
+ RISAB_NUMBER_OF_PAGES_MAX);
+ ret = -EINVAL;
+ goto err_clk_disable;
+ }
+
+ ret = nb_page;
+
+err_clk_disable:
+ clk_disable_unprepare(pdata->clk);
+
+ return ret;
+}
+
+static int stm32_risab_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct risab_pdata *pdata;
+ struct resource *res;
+ void __iomem *mmio;
+ int err, nb_pages;
+ struct clk *clk;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(mmio))
+ return PTR_ERR(mmio);
+
+ pdata->phys_base = res->start;
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Failed to get clk\n");
+
+ pdata->base = mmio;
+ pdata->clk = clk;
+ pdata->dev = &pdev->dev;
+
+ err = of_property_read_u32(np, "st,mem-map", &pdata->risab_map_base);
+ if (err) {
+ return dev_err_probe(&pdev->dev, err,
+ "Couldn't read the memory range covered by the RISAB\n");
+ }
+
+ nb_pages = stm32_risab_get_nb_pages(pdata);
+ if (nb_pages < 0)
+ return dev_err_probe(&pdev->dev, nb_pages, "Couldn't read RISAB number of pages\n");
+
+ pdata->nb_pages = nb_pages;
+
+ platform_set_drvdata(pdev, pdata);
+
+ return stm32_risab_register_debugfs(pdata);
+}
+
+static void stm32_risab_remove(struct platform_device *pdev)
+{
+ struct risab_pdata *pdata = platform_get_drvdata(pdev);
+
+ debugfs_remove(pdata->dbg_entry);
+}
+
+static const struct of_device_id stm32_risab_match[] = {
+ { .compatible = "st,stm32mp25-risab", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_risab_match);
+
+static struct platform_driver stm32_risab_driver = {
+ .probe = stm32_risab_probe,
+ .remove = stm32_risab_remove,
+ .driver = {
+ .name = "stm32-risab",
+ .of_match_table = stm32_risab_match,
+ },
+};
+module_platform_driver(stm32_risab_driver);
+
+MODULE_AUTHOR("Gatien Chevallier <gatien.chevallier@foss.st.com>");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/9] bus: rifsc: use new CONFIG_STM32_FIREWALL_DEBUG switch
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 1/9] dt-bindings: bus: document the RISAB firewall peripheral Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 2/9] bus: add RISAB dump debug driver Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 17:29 ` kernel test robot
2026-02-12 10:10 ` [PATCH v2 4/9] arm64: dts: st: add RISAB1/2/3/4/5/6 nodes to stm32mp251.dtsi Gatien Chevallier
` (5 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
Instead on relying on CONFIG_DEBUG_FS, rely on the new
CONFIG_STM32_FIREWALL_DEBUG switch that groups all stm32 firewall
debug features to embed RIFSC configuration dump.
While there, use IF_DEFINED() instead of #if defined() so that
all the code is always compiled and let the compiler optimize.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
drivers/bus/stm32_rifsc.c | 48 +++++++++++++++++++++++------------------------
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c
index debeaf8ea1bd..80bd5c5acfb4 100644
--- a/drivers/bus/stm32_rifsc.c
+++ b/drivers/bus/stm32_rifsc.c
@@ -73,7 +73,6 @@
#define RIF_CID0 0x0
#define RIF_CID1 0x1
-#if defined(CONFIG_DEBUG_FS)
#define RIFSC_RISUP_ENTRIES 128
#define RIFSC_RIMU_ENTRIES 16
#define RIFSC_RISAL_SUBREGIONS 2
@@ -434,18 +433,19 @@ struct rifsc_dbg_private {
unsigned int nb_risal;
};
-static const struct stm32_rifsc_resources_names rifsc_mp21_res_names = {
+static const struct __maybe_unused stm32_rifsc_resources_names rifsc_mp21_res_names = {
.device_names = stm32mp21_rifsc_risup_names,
.initiator_names = stm32mp21_rifsc_rimu_names,
};
-static const struct stm32_rifsc_resources_names rifsc_mp25_res_names = {
+static const struct __maybe_unused stm32_rifsc_resources_names rifsc_mp25_res_names = {
.device_names = stm32mp25_rifsc_risup_names,
.initiator_names = stm32mp25_rifsc_rimu_names,
};
-static void stm32_rifsc_fill_rimu_dbg_entry(struct rifsc_dbg_private *rifsc,
- struct rifsc_rimu_debug_data *dbg_entry, int i)
+static void __maybe_unused stm32_rifsc_fill_rimu_dbg_entry(struct rifsc_dbg_private *rifsc,
+ struct rifsc_rimu_debug_data *dbg_entry,
+ int i)
{
const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names;
u32 rimc_attr = readl_relaxed(rifsc->mmio + RIFSC_RIMC_ATTR0 + 0x4 * i);
@@ -457,8 +457,9 @@ static void stm32_rifsc_fill_rimu_dbg_entry(struct rifsc_dbg_private *rifsc,
dbg_entry->m_priv = rimc_attr & RIFSC_RIMC_MPRIV;
}
-static void stm32_rifsc_fill_dev_dbg_entry(struct rifsc_dbg_private *rifsc,
- struct rifsc_risup_debug_data *dbg_entry, int i)
+static void __maybe_unused stm32_rifsc_fill_dev_dbg_entry(struct rifsc_dbg_private *rifsc,
+ struct rifsc_risup_debug_data *dbg_entry,
+ int i)
{
const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names;
u32 cid_cfgr, sec_cfgr, priv_cfgr;
@@ -481,9 +482,9 @@ static void stm32_rifsc_fill_dev_dbg_entry(struct rifsc_dbg_private *rifsc,
}
-static void stm32_rifsc_fill_subreg_dbg_entry(struct rifsc_dbg_private *rifsc,
- struct rifsc_subreg_debug_data *dbg_entry, int i,
- int j)
+static void __maybe_unused
+stm32_rifsc_fill_subreg_dbg_entry(struct rifsc_dbg_private *rifsc,
+ struct rifsc_subreg_debug_data *dbg_entry, int i, int j)
{
u32 risc_xcfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG0_ACFGR + 0x10 * i + 0x8 * j);
u32 risc_xaddr;
@@ -503,7 +504,7 @@ static void stm32_rifsc_fill_subreg_dbg_entry(struct rifsc_dbg_private *rifsc,
}
}
-static int stm32_rifsc_conf_dump_show(struct seq_file *s, void *data)
+static int __maybe_unused stm32_rifsc_conf_dump_show(struct seq_file *s, void *data)
{
struct rifsc_dbg_private *rifsc = (struct rifsc_dbg_private *)s->private;
int i, j;
@@ -603,8 +604,9 @@ static int stm32_rifsc_conf_dump_show(struct seq_file *s, void *data)
}
DEFINE_SHOW_ATTRIBUTE(stm32_rifsc_conf_dump);
-static int stm32_rifsc_register_debugfs(struct stm32_firewall_controller *rifsc_controller,
- u32 nb_risup, u32 nb_rimu, u32 nb_risal)
+static int __maybe_unused
+stm32_rifsc_register_debugfs(struct stm32_firewall_controller *rifsc_controller, u32 nb_risup,
+ u32 nb_rimu, u32 nb_risal)
{
struct rifsc_dbg_private *rifsc_priv;
struct dentry *root = NULL;
@@ -630,7 +632,6 @@ static int stm32_rifsc_register_debugfs(struct stm32_firewall_controller *rifsc_
return 0;
}
-#endif /* defined(CONFIG_DEBUG_FS) */
static bool stm32_rifsc_is_semaphore_available(void __iomem *addr)
{
@@ -800,11 +801,12 @@ static int stm32_rifsc_probe(struct platform_device *pdev)
return rc;
}
-#if defined(CONFIG_DEBUG_FS)
- rc = stm32_rifsc_register_debugfs(rifsc_controller, nb_risup, nb_rimu, nb_risal);
- if (rc)
- return dev_err_probe(rifsc_controller->dev, rc, "Failed creating debugfs entry\n");
-#endif
+ if (IS_ENABLED(CONFIG_STM32_FIREWALL_DEBUG)) {
+ rc = stm32_rifsc_register_debugfs(rifsc_controller, nb_risup, nb_rimu, nb_risal);
+ if (rc)
+ return dev_err_probe(rifsc_controller->dev, rc,
+ "Failed creating debugfs entry\n");
+ }
/* Populate all allowed nodes */
return of_platform_populate(np, NULL, NULL, &pdev->dev);
@@ -813,15 +815,11 @@ static int stm32_rifsc_probe(struct platform_device *pdev)
static const struct of_device_id stm32_rifsc_of_match[] = {
{
.compatible = "st,stm32mp25-rifsc",
-#if defined(CONFIG_DEBUG_FS)
- .data = &rifsc_mp25_res_names,
-#endif
+ .data = PTR_IF(IS_ENABLED(CONFIG_STM32_FIREWALL_DEBUG), &rifsc_mp25_res_names),
},
{
.compatible = "st,stm32mp21-rifsc",
-#if defined(CONFIG_DEBUG_FS)
- .data = &rifsc_mp21_res_names,
-#endif
+ .data = PTR_IF(IS_ENABLED(CONFIG_STM32_FIREWALL_DEBUG), &rifsc_mp21_res_names)
},
{}
};
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/9] bus: rifsc: use new CONFIG_STM32_FIREWALL_DEBUG switch
2026-02-12 10:10 ` [PATCH v2 3/9] bus: rifsc: use new CONFIG_STM32_FIREWALL_DEBUG switch Gatien Chevallier
@ 2026-02-12 17:29 ` kernel test robot
0 siblings, 0 replies; 12+ messages in thread
From: kernel test robot @ 2026-02-12 17:29 UTC (permalink / raw)
To: Gatien Chevallier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Michael Turquette,
Stephen Boyd
Cc: llvm, oe-kbuild-all, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, linux-clk, Gatien Chevallier
Hi Gatien,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 05f7e89ab9731565d8a62e3b5d1ec206485eeb0b]
url: https://github.com/intel-lab-lkp/linux/commits/Gatien-Chevallier/dt-bindings-bus-document-the-RISAB-firewall-peripheral/20260212-182006
base: 05f7e89ab9731565d8a62e3b5d1ec206485eeb0b
patch link: https://lore.kernel.org/r/20260212-stm32_risab-v2-3-02ef2859b596%40foss.st.com
patch subject: [PATCH v2 3/9] bus: rifsc: use new CONFIG_STM32_FIREWALL_DEBUG switch
config: loongarch-randconfig-002-20260212 (https://download.01.org/0day-ci/archive/20260213/202602130151.3v3igg2M-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
rustc: rustc 1.88.0 (6b00bc388 2025-06-23)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260213/202602130151.3v3igg2M-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602130151.3v3igg2M-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/bus/stm32_rifsc.c:436:21: warning: attribute declaration must precede definition [-Wignored-attributes]
436 | static const struct __maybe_unused stm32_rifsc_resources_names rifsc_mp21_res_names = {
| ^
include/linux/compiler_attributes.h:343:56: note: expanded from macro '__maybe_unused'
343 | #define __maybe_unused __attribute__((__unused__))
| ^
drivers/bus/stm32_rifsc.c:424:8: note: previous definition is here
424 | struct stm32_rifsc_resources_names {
| ^
drivers/bus/stm32_rifsc.c:441:21: warning: attribute declaration must precede definition [-Wignored-attributes]
441 | static const struct __maybe_unused stm32_rifsc_resources_names rifsc_mp25_res_names = {
| ^
include/linux/compiler_attributes.h:343:56: note: expanded from macro '__maybe_unused'
343 | #define __maybe_unused __attribute__((__unused__))
| ^
drivers/bus/stm32_rifsc.c:424:8: note: previous definition is here
424 | struct stm32_rifsc_resources_names {
| ^
2 warnings generated.
vim +436 drivers/bus/stm32_rifsc.c
435
> 436 static const struct __maybe_unused stm32_rifsc_resources_names rifsc_mp21_res_names = {
437 .device_names = stm32mp21_rifsc_risup_names,
438 .initiator_names = stm32mp21_rifsc_rimu_names,
439 };
440
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/9] arm64: dts: st: add RISAB1/2/3/4/5/6 nodes to stm32mp251.dtsi
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
` (2 preceding siblings ...)
2026-02-12 10:10 ` [PATCH v2 3/9] bus: rifsc: use new CONFIG_STM32_FIREWALL_DEBUG switch Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 5/9] arm64: dts: st: add RISAB1/2/3/4/5/6 nodes to stm32mp231.dtsi Gatien Chevallier
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
Add RISAB1/2/3/4/5/6 nodes to the stm32mp251.dtsi device tree SoC
file.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 48 ++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index a8e6e0f77b83..b413430939a8 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -1733,6 +1733,54 @@ pcie@0,0 {
};
};
+ risab1: firewall@420f0000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x420f0000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa000000 0x20000>;
+ status = "disabled";
+ };
+
+ risab2: firewall@42100000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42100000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa020000 0x20000>;
+ status = "disabled";
+ };
+
+ risab3: firewall@42110000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42110000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa040000 0x20000>;
+ status = "disabled";
+ };
+
+ risab4: firewall@42120000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42120000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa060000 0x20000>;
+ status = "disabled";
+ };
+
+ risab5: firewall@42130000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42130000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa080000 0x20000>;
+ status = "disabled";
+ };
+
+ risab6: firewall@42140000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42140000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa0a0000 0x20000>;
+ status = "disabled";
+ };
+
bsec: efuse@44000000 {
compatible = "st,stm32mp25-bsec";
reg = <0x44000000 0x1000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/9] arm64: dts: st: add RISAB1/2/3/4/5/6 nodes to stm32mp231.dtsi
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
` (3 preceding siblings ...)
2026-02-12 10:10 ` [PATCH v2 4/9] arm64: dts: st: add RISAB1/2/3/4/5/6 nodes to stm32mp251.dtsi Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 6/9] arm64: dts: st: enable all RISAB instances on the stm32mp257f-ev1 board Gatien Chevallier
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
Add RISAB1/2/3/4/5/6 nodes to the stm32mp231.dtsi device tree SoC
file.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp231.dtsi | 48 ++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 88e214d395ab..326d4bd59f96 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -755,6 +755,54 @@ stmmac_axi_config_1: stmmac-axi-config {
};
};
+ risab1: firewall@420f0000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x420f0000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa000000 0x20000>;
+ status = "disabled";
+ };
+
+ risab2: firewall@42100000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42100000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa020000 0x20000>;
+ status = "disabled";
+ };
+
+ risab3: firewall@42110000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42110000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa040000 0x20000>;
+ status = "disabled";
+ };
+
+ risab4: firewall@42120000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42120000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa060000 0x20000>;
+ status = "disabled";
+ };
+
+ risab5: firewall@42130000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42130000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa080000 0x20000>;
+ status = "disabled";
+ };
+
+ risab6: firewall@42140000 {
+ compatible = "st,stm32mp25-risab";
+ reg = <0x42140000 0x1000>;
+ clocks = <&scmi_clk CK_SCMI_ICN_LS_MCU>;
+ st,mem-map = <0xa0a0000 0x20000>;
+ status = "disabled";
+ };
+
bsec: efuse@44000000 {
compatible = "st,stm32mp25-bsec";
reg = <0x44000000 0x1000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 6/9] arm64: dts: st: enable all RISAB instances on the stm32mp257f-ev1 board
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
` (4 preceding siblings ...)
2026-02-12 10:10 ` [PATCH v2 5/9] arm64: dts: st: add RISAB1/2/3/4/5/6 nodes to stm32mp231.dtsi Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 7/9] arm64: dts: st: enable all RISAB instances on the stm32mp257f-dk board Gatien Chevallier
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
To be able to dump the RISAB configurations, enable all RISAB instances
on the stm32mp257f-ev1 board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index bb6d6393d2e4..973acea6d248 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -352,6 +352,30 @@ pcie@0,0 {
};
};
+&risab1 {
+ status = "okay";
+};
+
+&risab2 {
+ status = "okay";
+};
+
+&risab3 {
+ status = "okay";
+};
+
+&risab4 {
+ status = "okay";
+};
+
+&risab5 {
+ status = "okay";
+};
+
+&risab6 {
+ status = "okay";
+};
+
&rtc {
status = "okay";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 7/9] arm64: dts: st: enable all RISAB instances on the stm32mp257f-dk board
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
` (5 preceding siblings ...)
2026-02-12 10:10 ` [PATCH v2 6/9] arm64: dts: st: enable all RISAB instances on the stm32mp257f-ev1 board Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 8/9] arm64: dts: st: enable all RISAB instances on the stm32mp235f-dk board Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 9/9] MAINTAINERS: add entries to maintained stm32 firewall files Gatien Chevallier
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
To be able to dump the RISAB configurations, enable all RISAB instances
on the stm32mp257f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
index e718d888ce21..42894ba954cc 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
@@ -100,6 +100,30 @@ phy1_eth1: ethernet-phy@1 {
};
};
+&risab1 {
+ status = "okay";
+};
+
+&risab2 {
+ status = "okay";
+};
+
+&risab3 {
+ status = "okay";
+};
+
+&risab4 {
+ status = "okay";
+};
+
+&risab5 {
+ status = "okay";
+};
+
+&risab6 {
+ status = "okay";
+};
+
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 8/9] arm64: dts: st: enable all RISAB instances on the stm32mp235f-dk board
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
` (6 preceding siblings ...)
2026-02-12 10:10 ` [PATCH v2 7/9] arm64: dts: st: enable all RISAB instances on the stm32mp257f-dk board Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
2026-02-12 10:10 ` [PATCH v2 9/9] MAINTAINERS: add entries to maintained stm32 firewall files Gatien Chevallier
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
To be able to dump the RISAB configurations, enable all RISAB instances
on the stm32mp235f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
index c3e688068223..b76549b9f64b 100644
--- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
@@ -100,6 +100,30 @@ phy1_eth1: ethernet-phy@1 {
};
};
+&risab1 {
+ status = "okay";
+};
+
+&risab2 {
+ status = "okay";
+};
+
+&risab3 {
+ status = "okay";
+};
+
+&risab4 {
+ status = "okay";
+};
+
+&risab5 {
+ status = "okay";
+};
+
+&risab6 {
+ status = "okay";
+};
+
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 9/9] MAINTAINERS: add entries to maintained stm32 firewall files
2026-02-12 10:10 [PATCH v2 0/9] drivers: bus: add RISAB dump debug driver Gatien Chevallier
` (7 preceding siblings ...)
2026-02-12 10:10 ` [PATCH v2 8/9] arm64: dts: st: enable all RISAB instances on the stm32mp235f-dk board Gatien Chevallier
@ 2026-02-12 10:10 ` Gatien Chevallier
8 siblings, 0 replies; 12+ messages in thread
From: Gatien Chevallier @ 2026-02-12 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-clk, Gatien Chevallier
Add documentation and risa* entries to maintained stm32 firewall files.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
MAINTAINERS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e08767323763..316fcffcc094 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24734,9 +24734,13 @@ F: drivers/power/supply/stc3117_fuel_gauge.c
ST STM32 FIREWALL
M: Gatien Chevallier <gatien.chevallier@foss.st.com>
S: Maintained
+F: Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
+F: Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
+F: Documentation/devicetree/bindings/bus/st,stm32mp25-risab.yaml
F: drivers/bus/stm32_etzpc.c
F: drivers/bus/stm32_firewall.c
F: drivers/bus/stm32_rifsc.c
+F: drivers/bus/stm32_risa*.c
ST STM32 HDP PINCTRL DRIVER
M: Clément Le Goffic <legoffic.clement@gmail.com>
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread