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Mon, 23 Feb 2026 22:03:48 -0800 From: Akhil R To: CC: , , , , , , , , , , , , Subject: Re: [PATCH 5/8] dmaengine: tegra: Support address width > 40 bits Date: Tue, 24 Feb 2026 11:33:47 +0530 Message-ID: <20260224060347.45544-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|LV8PR12MB9183:EE_ X-MS-Office365-Filtering-Correlation-Id: daebbc03-2efa-4d3f-7d6a-08de736a85f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZSEVah6caOntnCkJww9F2P45m+Z1lEZMT5X7hK9LSYnt3dUfhClYwkx39rUn?= =?us-ascii?Q?6HsvuVD5o+ouqtLYUc06itHZKaV9NJvq29EgEqq6GWMWr48gxPyIgflfUh4M?= =?us-ascii?Q?LQ6YE26LxZ6DD8Ob7WjXn3M5GWsSfppIVWn1u09ZZ1qNqhm7M9DPtbZtQCBT?= =?us-ascii?Q?C1UUj9dKs4ruDdDCxGkMZpQaQZV+4OCYmQFd0SezayWpAH3fE66KHEYjvIXI?= =?us-ascii?Q?lILf2UbVI7n2Ap9isxwTIFRh9nGI4JXFM7qsS+qg8rThuKOb1lpYHznj8akp?= =?us-ascii?Q?3HcECFV48h0pVUrDWUeGfWLPCZ1xuTAnoAxpQMw63nA6JrKRQACBkKxqVfpX?= =?us-ascii?Q?xcntCb5KyymQKeE75RIhmJs05AoPw+1qEMIW87uO9WdQZNeXBdOafWLoVFyO?= =?us-ascii?Q?DzuPKPJ3gZqPXc6lf5v6HNb7JsGa2ewuxBA+6+m0W1jELgDKsM6Ga56uxEE+?= =?us-ascii?Q?RhIEVIKXKUo7nbCKUNfTxfqIwBl7AZY/B6d00qi112oLLMT2+jFl8JiP25Dr?= =?us-ascii?Q?OSh0nLPhPOUXFlJ0rRNcN+drRFXh828DHyGefvNipSF5H9gaYGSI8GSTd+xh?= =?us-ascii?Q?WSDLD79f2zq8zJ+kyDeH+3D+JOWfb+jLYKIGb6BVhye/2eT511tAzgo0dyA7?= =?us-ascii?Q?Cu1942bPNthpmB+XUsSKOknlW9EDcYsA99e8AnGXCUv4YLC/59AUGv+AVGHU?= =?us-ascii?Q?CEcsPbvNAJDLjgHITLfs/3v3JIbdMOr6dYWI+FnnVeWcCHyGdURDhk1V67+5?= =?us-ascii?Q?XvosDb5/qAYVxxqXGUaqXrB8rVX7Zf2nxH52EMok6OyfYr+0GlrTP4yabEk1?= =?us-ascii?Q?TiCjgXoUM0WVk5LTImib90BtNUKTUILyF8rmWwc2Gn3vihtLE79kqrzMFMkg?= =?us-ascii?Q?v26iDFjerwKevAO07SVnBuhTh7gzGemwrMI7RlVb9SraeTIOx7PLsTHP0M6H?= =?us-ascii?Q?2kErwObNHKMUTPHN7v4PYFw8Z17bjXImbGd4INgHWTAUjfKNbPkr5l2K9S0a?= =?us-ascii?Q?brTVOahe2wuIhYCZFrX0ONrR/hJ4nl5zjuZXEGP1/xAtlSFGjoPKjBnmB7Qz?= =?us-ascii?Q?9qIWFR3oYSybmpoavvC4vJ/2auEEMiwIWgrlcs26IuN+/stbTOBFbfV7eWeV?= =?us-ascii?Q?hV1JpaqKjBQM2RidCCwPNIo1GgVq7OCMPyW377E3GsPZb0lPbn3kGW4YgN1+?= =?us-ascii?Q?80fGTEs7fdY8v03W/PstBh39kKGZnBfcVZ1YH0/WgXycsVEfT3UOY+jKhMsX?= =?us-ascii?Q?ZVMYmZLBezqytotyu52zmWKE2sO7yOieoxoiVXRmoXpcJKSwJCvrQV+jIKqw?= =?us-ascii?Q?As6OilZ8JiI/wtrWUPmIMU4Z3TIEk4y2rgwIbU6rYyxMjfeLEVAI5NWOiRC5?= =?us-ascii?Q?YKAnrvnWSqX2Z0jVExh+EaftlB8BUys52aFGqYjuaFJAhdpeF66EKiq8yBpC?= =?us-ascii?Q?SAn25VeGaKE76he85k1xAoH8Oa5Cb7gCxVSOjmuR9m1FqB7dm9eEJKBMQfrM?= =?us-ascii?Q?mPXhPlqDFuzA8Igv0t59gG08Gyujw1q03Z81LgB3xDxnkGuq0dWcpP0pX3/6?= =?us-ascii?Q?8lRwVsYWFI2EhtyD/rVDf+R4VtMOYU2K6lvbDxKehzGfPU6n2iGSoSmvyOv2?= =?us-ascii?Q?S90HtuRVf1xYJqDszgtXzaM9cXVx0pvv68o9oUF6NPKsjqc7yYLitY2JIjIs?= =?us-ascii?Q?TUkusw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2V2I0TPufv0L5zoYgaVaqhdh8v1nA1HqBl3+eVK903BIFhV+ssbTB1Trcy5yF7R/+5RT8OLWq2uK/02U1uJa+RuqeYyNTXQEXaaPFG2yHqsxqr8PRPeGwNG88sZ5dwjonAxK1pV+hAFNs0S3NGq1x2Q742/iwBnWhEuR0fH4Ik+0zyOGxJB7cyk0cmRd1+tm0uMu86LyQUEgVm0qpMPzL9KmrZfe1ySNGnYh5ve2Xo68MYAqNH++qxd9kWrNF6jpaSUm28ijH2/Hq1dTD9GH7BKdtX0N9HExYyKvJyAXCuBSU6OsjRnhCxpEwdIYBRZjXmiI9xCPl8qZsz2k8KCS95KsjA+BfISdaQooTk9+TWHaLcluhJhFmyMyYKZMkdMnoW2AD5G12ar8v2UOzMHVbCTof4BeEaLu8RHrNnEA+0iXDWusXYickDhnBA38p3B9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2026 06:04:08.2380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: daebbc03-2efa-4d3f-7d6a-08de736a85f4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9183 On Tue, 17 Feb 2026 14:44:28 -0500 Frank Li wrote: > On Tue, Feb 17, 2026 at 11:04:54PM +0530, Akhil R wrote: >> Tegra264 supports address width of 41 bits and has a separate register >> to accommodate the high address. Add a device data property to specify >> the number of address bits supported on a device and use that to >> program the required registers. >> >> Signed-off-by: Akhil R >> --- >> drivers/dma/tegra186-gpc-dma.c | 129 +++++++++++++++++++++------------ >> 1 file changed, 82 insertions(+), 47 deletions(-) >> >> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c >> index 72701b543ceb..ce3b1dd52bb3 100644 >> --- a/drivers/dma/tegra186-gpc-dma.c >> +++ b/drivers/dma/tegra186-gpc-dma.c >> @@ -151,6 +151,7 @@ struct tegra_dma_channel; >> */ >> struct tegra_dma_chip_data { >> bool hw_support_pause; >> + unsigned int addr_bits; >> unsigned int nr_channels; >> unsigned int channel_reg_size; >> unsigned int max_dma_count; >> @@ -166,6 +167,8 @@ struct tegra_dma_channel_regs { >> u32 src; >> u32 dst; >> u32 high_addr; >> + u32 src_high; >> + u32 dst_high; >> u32 mc_seq; >> u32 mmio_seq; >> u32 wcount; >> @@ -189,7 +192,8 @@ struct tegra_dma_sg_req { >> u32 csr; >> u32 src; >> u32 dst; >> - u32 high_addr; >> + u32 src_high; >> + u32 dst_high; >> u32 mc_seq; >> u32 mmio_seq; >> u32 wcount; >> @@ -273,6 +277,41 @@ static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) >> return tdc->vc.chan.device->dev; >> } >> >> +static void tegra_dma_program_addr(struct tegra_dma_channel *tdc, >> + struct tegra_dma_sg_req *sg_req) >> +{ >> + tdc_write(tdc, tdc->regs->src, sg_req->src); >> + tdc_write(tdc, tdc->regs->dst, sg_req->dst); >> + >> + if (tdc->tdma->chip_data->addr_bits > 40) { >> + tdc_write(tdc, tdc->regs->src_high, >> + sg_req->src_high); >> + tdc_write(tdc, tdc->regs->dst_high, >> + sg_req->dst_high); >> + } else { >> + tdc_write(tdc, tdc->regs->high_addr, >> + sg_req->src_high | sg_req->dst_high); >> + } >> +} >> + >> +static void tegra_dma_configure_addr(struct tegra_dma_channel *tdc, >> + struct tegra_dma_sg_req *sg_req, >> + phys_addr_t src, phys_addr_t dst) >> +{ >> + sg_req->src = lower_32_bits(src); >> + sg_req->dst = lower_32_bits(dst); > > I suggest save 64bit address to sq_req. In tegra_dma_program_addr() to > handle difference between 40bit and 41bit. > > So only need handle difference at one place. Ack. Will update. Regards, Akhil