From: Chaoyi Chen <kernel@airkyi.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Alexey Charkov <alchark@gmail.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Chaoyi Chen <chaoyi.chen@rock-chips.com>,
Andy Yan <andy.yan@rock-chips.com>,
Sebastian Reichel <sebastian.reichel@collabora.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: rockchip: Enable displayport for rk3576 evb2
Date: Tue, 24 Feb 2026 16:38:18 +0800 [thread overview]
Message-ID: <20260224083818.109-1-kernel@airkyi.com> (raw)
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The rk3576 evb2 has a full size displayport connector. Enable it.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
---
.../boot/dts/rockchip/rk3576-evb2-v10.dts | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts
index 028fb0a830b2..6bdc232ab267 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts
@@ -27,6 +27,19 @@ chosen {
stdout-path = "serial0:1500000n8";
};
+ dp-con {
+ compatible = "dp-connector";
+ dp-pwr-supply = <&vcc3v3_dp_port>;
+ label = "DP OUT";
+ type = "full-size";
+
+ port {
+ dp0_con_in: endpoint {
+ remote-endpoint = <&dp0_out_con>;
+ };
+ };
+ };
+
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -312,6 +325,24 @@ &combphy1_psu {
status = "okay";
};
+&dp {
+ pinctrl-0 = <&dpm0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&dp0_in {
+ dp0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dp0>;
+ };
+};
+
+&dp0_out {
+ dp0_out_con: endpoint {
+ remote-endpoint = <&dp0_con_in>;
+ };
+};
+
&gmac0 {
clock_in_out = "output";
phy-mode = "rgmii-id";
@@ -1005,6 +1036,17 @@ hub_2_0: hub@1 {
};
&vop {
+ /*
+ * If no dedicated PLL was specified, the GPLL would be automatically
+ * assigned as the PLL source for dclk_vp1_src. As the frequency of GPLL
+ * is 1188 MHz, we can only get typical clock frequencies such as
+ * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
+ *
+ * So here we set the parent clock of VP1 to VPLL so that we can get
+ * any frequency.
+ */
+ assigned-clocks = <&cru DCLK_VP1_SRC>;
+ assigned-clock-parents = <&cru PLL_VPLL>;
status = "okay";
};
@@ -1018,3 +1060,10 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi_in_vp0>;
};
};
+
+&vp1 {
+ vp1_out_dp0: endpoint@a {
+ reg = <ROCKCHIP_VOP2_EP_DP0>;
+ remote-endpoint = <&dp0_in_vp1>;
+ };
+};
--
2.51.1
next reply other threads:[~2026-02-24 8:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-24 8:38 Chaoyi Chen [this message]
2026-03-02 12:58 ` [PATCH] arm64: dts: rockchip: Enable displayport for rk3576 evb2 Heiko Stuebner
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