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Tue, 24 Feb 2026 04:20:59 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 5/5] PCI: tegra: Use BIT() and GENMASK() macros for register definitions Date: Tue, 24 Feb 2026 17:49:01 +0530 Message-ID: <20260224121948.25218-6-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Replace manual bit operations with standard BIT() and GENMASK() macros. This eliminates magic numbers, enhances readability, improves maintainability, and resolves checkpatch.pl warnings. Cc: Jon Hunter Signed-off-by: Anand Moon --- v3: None v2: improve the commit message v1: New patch --- drivers/pci/controller/pci-tegra.c | 129 +++++++++++++++-------------- 1 file changed, 65 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 459a2bb1a065..2c806404f572 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -13,6 +13,7 @@ * Author: Thierry Reding */ +#include #include #include #include @@ -85,17 +86,17 @@ #define AFI_MSI_EN_VEC(x) (0x8c + ((x) * 4)) #define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) -#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31) +#define AFI_CONFIGURATION_EN_FPCI BIT(0) +#define AFI_CONFIGURATION_CLKEN_OVERRIDE BIT(31) #define AFI_FPCI_ERROR_MASKS 0xb0 #define AFI_INTR_MASK 0xb4 -#define AFI_INTR_MASK_INT_MASK (1 << 0) -#define AFI_INTR_MASK_MSI_MASK (1 << 8) +#define AFI_INTR_MASK_INT_MASK BIT(0) +#define AFI_INTR_MASK_MSI_MASK BIT(8) #define AFI_INTR_CODE 0xb8 -#define AFI_INTR_CODE_MASK 0xf +#define AFI_INTR_CODE_MASK GENMASK(3, 0) #define AFI_INTR_INI_SLAVE_ERROR 1 #define AFI_INTR_INI_DECODE_ERROR 2 #define AFI_INTR_TARGET_ABORT 3 @@ -114,32 +115,32 @@ #define AFI_INTR_SIGNATURE 0xbc #define AFI_UPPER_FPCI_ADDRESS 0xc0 #define AFI_SM_INTR_ENABLE 0xc4 -#define AFI_SM_INTR_INTA_ASSERT (1 << 0) -#define AFI_SM_INTR_INTB_ASSERT (1 << 1) -#define AFI_SM_INTR_INTC_ASSERT (1 << 2) -#define AFI_SM_INTR_INTD_ASSERT (1 << 3) -#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) -#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) -#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) -#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) +#define AFI_SM_INTR_INTA_ASSERT BIT(0) +#define AFI_SM_INTR_INTB_ASSERT BIT(1) +#define AFI_SM_INTR_INTC_ASSERT BIT(2) +#define AFI_SM_INTR_INTD_ASSERT BIT(3) +#define AFI_SM_INTR_INTA_DEASSERT BIT(4) +#define AFI_SM_INTR_INTB_DEASSERT BIT(5) +#define AFI_SM_INTR_INTC_DEASSERT BIT(6) +#define AFI_SM_INTR_INTD_DEASSERT BIT(7) #define AFI_AFI_INTR_ENABLE 0xc8 -#define AFI_INTR_EN_INI_SLVERR (1 << 0) -#define AFI_INTR_EN_INI_DECERR (1 << 1) -#define AFI_INTR_EN_TGT_SLVERR (1 << 2) -#define AFI_INTR_EN_TGT_DECERR (1 << 3) -#define AFI_INTR_EN_TGT_WRERR (1 << 4) -#define AFI_INTR_EN_DFPCI_DECERR (1 << 5) -#define AFI_INTR_EN_AXI_DECERR (1 << 6) -#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) -#define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_INTR_EN_INI_SLVERR BIT(0) +#define AFI_INTR_EN_INI_DECERR BIT(1) +#define AFI_INTR_EN_TGT_SLVERR BIT(2) +#define AFI_INTR_EN_TGT_DECERR BIT(3) +#define AFI_INTR_EN_TGT_WRERR BIT(4) +#define AFI_INTR_EN_DFPCI_DECERR BIT(5) +#define AFI_INTR_EN_AXI_DECERR BIT(6) +#define AFI_INTR_EN_FPCI_TIMEOUT BIT(7) +#define AFI_INTR_EN_PRSNT_SENSE BIT(8) #define AFI_PCIE_PME 0xf0 #define AFI_PCIE_CONFIG 0x0f8 -#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) -#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe -#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) +#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) BIT((x) + 1) +#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL GENMASK(3, 1) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK GENMASK(23, 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) @@ -150,79 +151,79 @@ #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111 (0x2 << 20) -#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(x) (1 << ((x) + 29)) -#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL (0x7 << 29) +#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(x) BIT((x) + 29) +#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL GENMASK(31, 29) #define AFI_FUSE 0x104 -#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) +#define AFI_FUSE_PCIE_T0_GEN2_DIS BIT(2) #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 -#define AFI_PEX_CTRL_RST (1 << 0) -#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) -#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) -#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) +#define AFI_PEX_CTRL_RST BIT(0) +#define AFI_PEX_CTRL_CLKREQ_EN BIT(1) +#define AFI_PEX_CTRL_REFCLK_EN BIT(3) +#define AFI_PEX_CTRL_OVERRIDE_EN BIT(4) #define AFI_PLLE_CONTROL 0x160 -#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) -#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) +#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL BIT(9) +#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN BIT(1) #define AFI_PEXBIAS_CTRL_0 0x168 #define RP_ECTL_2_R1 0x00000e84 -#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff +#define RP_ECTL_2_R1_RX_CTLE_1C_MASK GENMASK(15, 0) #define RP_ECTL_4_R1 0x00000e8c -#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16) +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK GENMASK(31, 16) #define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16 #define RP_ECTL_5_R1 0x00000e90 -#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff +#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK GENMASK(31, 0) #define RP_ECTL_6_R1 0x00000e94 -#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff +#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK GENMASK(31, 0) #define RP_ECTL_2_R2 0x00000ea4 #define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff #define RP_ECTL_4_R2 0x00000eac -#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16) +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK GENMASK(31, 16) #define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16 #define RP_ECTL_5_R2 0x00000eb0 -#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff +#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK GENMASK(31, 0) #define RP_ECTL_6_R2 0x00000eb4 -#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff +#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK GENMASK(31, 0) #define RP_VEND_XP 0x00000f00 -#define RP_VEND_XP_DL_UP (1 << 30) -#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) -#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) -#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_XP_DL_UP BIT(30) +#define RP_VEND_XP_OPPORTUNISTIC_ACK BIT(27) +#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC BIT(28) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK GENMASK(25, 18) #define RP_VEND_CTL0 0x00000f44 -#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK GENMASK(15, 12) #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) #define RP_VEND_CTL1 0x00000f48 -#define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_CTL1_ERPT BIT(13) #define RP_VEND_XP_BIST 0x00000f4c -#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE BIT(28) #define RP_VEND_CTL2 0x00000fa8 -#define RP_VEND_CTL2_PCA_ENABLE (1 << 7) +#define RP_VEND_CTL2_PCA_ENABLE BIT(7) #define RP_PRIV_MISC 0x00000fe0 -#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) -#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) -#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16) +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT GENMASK(3, 1) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT GENMASK(3, 0) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK GENMASK(22, 16) #define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16) -#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) -#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE BIT(23) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK GENMASK(30, 24) #define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24) -#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE BIT(31) #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 @@ -233,22 +234,22 @@ #define PADS_CTL_SEL 0x0000009c #define PADS_CTL 0x000000a0 -#define PADS_CTL_IDDQ_1L (1 << 0) -#define PADS_CTL_TX_DATA_EN_1L (1 << 6) -#define PADS_CTL_RX_DATA_EN_1L (1 << 10) +#define PADS_CTL_IDDQ_1L BIT(0) +#define PADS_CTL_TX_DATA_EN_1L BIT(6) +#define PADS_CTL_RX_DATA_EN_1L BIT(10) #define PADS_PLL_CTL_TEGRA20 0x000000b8 #define PADS_PLL_CTL_TEGRA30 0x000000b4 -#define PADS_PLL_CTL_RST_B4SM (1 << 1) -#define PADS_PLL_CTL_LOCKDET (1 << 8) -#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) +#define PADS_PLL_CTL_RST_B4SM BIT(1) +#define PADS_PLL_CTL_LOCKDET BIT(8) +#define PADS_PLL_CTL_REFCLK_MASK GENMASK(17, 16) #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) -#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) +#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS BIT(16) #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) -#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) -#define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) +#define PADS_PLL_CTL_TXCLKREF_DIV5 BIT(20) +#define PADS_PLL_CTL_TXCLKREF_BUF_EN BIT(22) #define PADS_REFCLK_CFG0 0x000000c8 #define PADS_REFCLK_CFG1 0x000000cc -- 2.50.1