Re: [PATCH v3 1/2] dt-bindings: misc: xlnx,axi-fifo-mm-s: convert to json-schema

[Krzysztof Kozlowski <krzk@kernel.org>]

On Fri, Feb 27, 2026 at 05:08:43PM -0300, Lucas Faria Mendes wrote:
> Convert the Xilinx AXI-Stream FIFO IP core bindings from legacy text
> format to modern YAML json-schema.
> 
> While converting, the following changes were made:
> - Updated property types for 'xlnx,use-rx-data' and 'xlnx,use-tx-data'
>   from uint32 to boolean, as they represent hardware features.
> - Removed the rigid 32-bit constraint on data width properties to
>   better reflect hardware capabilities.
> - Renamed the example node to "fifo" to follow generic naming conventions.
> - Removed the legacy text binding file.

Last is not the change made in conversion. It is THE conversion. Drop.

You also dropped 15 more properties without any explanation!

> 
> Signed-off-by: Lucas Faria Mendes <lucas.fariamo08@gmail.com>
> ---
>  .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 95 ++++++++++++++++++
>  drivers/staging/axis-fifo/axis-fifo.txt       | 96 -------------------
>  2 files changed, 95 insertions(+), 96 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
>  delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt
> 
> diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> new file mode 100644
> index 000000000000..b3e6a2189289
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

You need to respond to previous review you received.

So again - isn't this DMA? or some part of Xilinx SoC? Or FPGA
interface? Because for sure this is not a "misc" device.


> @@ -0,0 +1,95 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx AXI-Stream FIFO IP core
> +
> +maintainers:
> +  - Jacob Feder <jacobsfeder@gmail.com>
> +
> +description: |
> +  The Xilinx AXI-Stream FIFO IP core has read and write AXI-Stream FIFOs,
> +  the contents of which can be accessed from the AXI4 memory-mapped interface.
> +  This is useful for transferring data from a processor into the FPGA fabric.
> +
> +  See Xilinx PG080 document for IP details.
> +
> +  Currently supports only store-forward mode with a 32-bit AXI4-Lite
> +  interface.

Binding describes hardware, so are you saying hardware supports it or
what exactly?

> +
> +properties:
> +  compatible:
> +    enum:
> +      - xlnx,axi-fifo-mm-s-4.1
> +      - xlnx,axi-fifo-mm-s-4.2
> +      - xlnx,axi-fifo-mm-s-4.3
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-names:
> +    items:
> +      - const: interrupt

Pointless name, drop completely interrupt-names.

> +
> +  xlnx,axi-str-rxd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 32
> +    description:
> +      AXI-Stream RX data width in bits. Only 32-bit is supported.

1. Const? So drop it. You don't need that property at all. Plus I don't
get why "supported" matters for us - supported by who?

2. Outstaging a binding means you do not preserve ABI but go via regular
review, thus: Use standard properties, like bus-width etc. See
dt-schema.

> +
> +  xlnx,axi-str-txd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 32
> +    description:
> +      AXI-Stream TX data width in bits. Only 32-bit is supported.
> +
> +  xlnx,rx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of RX FIFO in words.
> +
> +  xlnx,tx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of TX FIFO in words.
> +
> +  xlnx,use-rx-data:
> +    type: boolean
> +    description: RX FIFO is enabled.
> +
> +  xlnx,use-tx-data:
> +    type: boolean
> +    description: TX FIFO is enabled.

I don't get why do you need properties to enable TX or RX. Is there any
IP without one?

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - xlnx,axi-str-rxd-tdata-width
> +  - xlnx,axi-str-txd-tdata-width
> +  - xlnx,rx-fifo-depth
> +  - xlnx,tx-fifo-depth
> +  - xlnx,use-tx-data
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    fifo@43c00000 {
> +        compatible = "xlnx,axi-fifo-mm-s-4.1";
> +        reg = <0x43c00000 0x10000>;
> +        interrupt-names = "interrupt";
> +        interrupt-parent = <&intc>;
> +        interrupts = <0 29 4>;

Use proper defines.

Best regards,
Krzysztof