From: Pengyu Luo <mitltlatltl@gmail.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Krishna Manikandan <quic_mkrishn@quicinc.com>,
Jonathan Marek <jonathan@marek.ca>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Tianyu Gao <gty0622@gmail.com>,
White Lewis <liu224806@gmail.com>,
Pengyu Luo <mitltlatltl@gmail.com>
Subject: [PATCH v3 4/4] arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
Date: Sat, 28 Feb 2026 22:17:15 +0800 [thread overview]
Message-ID: <20260228141715.35307-5-mitltlatltl@gmail.com> (raw)
In-Reply-To: <20260228141715.35307-1-mitltlatltl@gmail.com>
The DT configuration follows other Samsung 5nm-based Qualcomm SOCs,
utilizing the same register layouts and clock structures.
However, DSI won't work properly for now until we submit dispcc fixes.
And some DSC enabled panels require DPU timing calculation fixes too.
(hdisplay / width timing round errors cause the fifo error)
Co-developed-by: Tianyu Gao <gty0622@gmail.com>
Signed-off-by: Tianyu Gao <gty0622@gmail.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Tested-by: White Lewis <liu224806@gmail.com> # HUAWEI Gaokun3
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 404 ++++++++++++++++++++++++-
1 file changed, 396 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 706eb1309..1599d698b 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -4652,13 +4653,31 @@ ports {
port@0 {
reg = <0>;
+
mdss0_intf0_out: endpoint {
remote-endpoint = <&mdss0_dp0_in>;
};
};
+ port@1 {
+ reg = <1>;
+
+ mdss0_intf1_out: endpoint {
+ remote-endpoint = <&mdss0_dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mdss0_intf2_out: endpoint {
+ remote-endpoint = <&mdss0_dsi1_in>;
+ };
+ };
+
port@4 {
reg = <4>;
+
mdss0_intf4_out: endpoint {
remote-endpoint = <&mdss0_dp1_in>;
};
@@ -4666,6 +4685,7 @@ mdss0_intf4_out: endpoint {
port@5 {
reg = <5>;
+
mdss0_intf5_out: endpoint {
remote-endpoint = <&mdss0_dp3_in>;
};
@@ -4673,6 +4693,7 @@ mdss0_intf5_out: endpoint {
port@6 {
reg = <6>;
+
mdss0_intf6_out: endpoint {
remote-endpoint = <&mdss0_dp2_in>;
};
@@ -4791,6 +4812,189 @@ opp-810000000 {
};
};
+ mdss0_dsi0: dsi@ae94000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <4>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss0_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss0_dsi0_in: endpoint {
+ remote-endpoint = <&mdss0_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss0_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss0_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm"
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss0_dsi1: dsi@ae96000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <5>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss0_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss0_dsi1_in: endpoint {
+ remote-endpoint = <&mdss0_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss0_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss0_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm"
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss0_dp1: displayport-controller@ae98000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0xae98000 0 0x200>,
@@ -5080,10 +5284,10 @@ dispcc0: clock-controller@af00000 {
<&mdss0_dp2_phy 1>,
<&mdss0_dp3_phy 0>,
<&mdss0_dp3_phy 1>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
@@ -6011,13 +6215,31 @@ ports {
port@0 {
reg = <0>;
+
mdss1_intf0_out: endpoint {
remote-endpoint = <&mdss1_dp0_in>;
};
};
+ port@1 {
+ reg = <1>;
+
+ mdss1_intf1_out: endpoint {
+ remote-endpoint = <&mdss1_dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mdss1_intf2_out: endpoint {
+ remote-endpoint = <&mdss1_dsi1_in>;
+ };
+ };
+
port@4 {
reg = <4>;
+
mdss1_intf4_out: endpoint {
remote-endpoint = <&mdss1_dp1_in>;
};
@@ -6025,6 +6247,7 @@ mdss1_intf4_out: endpoint {
port@5 {
reg = <5>;
+
mdss1_intf5_out: endpoint {
remote-endpoint = <&mdss1_dp3_in>;
};
@@ -6032,6 +6255,7 @@ mdss1_intf5_out: endpoint {
port@6 {
reg = <6>;
+
mdss1_intf6_out: endpoint {
remote-endpoint = <&mdss1_dp2_in>;
};
@@ -6147,6 +6371,170 @@ opp-810000000 {
};
};
+ mdss1_dsi0: dsi@22094000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x22094000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <4>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss1_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dsi0_in: endpoint {
+ remote-endpoint = <&mdss1_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss1_dsi0_phy: phy@22094400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm"
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x22094400 0 0x200>,
+ <0 0x22094600 0 0x280>,
+ <0 0x22094900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss1_dsi1: dsi@22096000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x22096000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <5>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc1 DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss1_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dsi1_in: endpoint {
+ remote-endpoint = <&mdss1_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss1_dsi1_phy: phy@22096400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm"
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x22096400 0 0x200>,
+ <0 0x22096600 0 0x280>,
+ <0 0x22096900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss1_dp1: displayport-controller@22098000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0x22098000 0 0x200>,
@@ -6434,10 +6822,10 @@ dispcc1: clock-controller@22100000 {
<&mdss1_dp2_phy 1>,
<&mdss1_dp3_phy 0>,
<&mdss1_dp3_phy 1>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
--
2.53.0
next prev parent reply other threads:[~2026-02-28 14:19 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-28 14:17 [PATCH v3 0/4] Add DSI display support for SC8280XP Pengyu Luo
2026-02-28 14:17 ` [PATCH v3 1/4] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP Pengyu Luo
2026-03-01 11:42 ` Krzysztof Kozlowski
2026-02-28 14:17 ` [PATCH v3 2/4] dt-bindings: display/msm: dsi-controller-main: " Pengyu Luo
2026-03-01 11:46 ` Krzysztof Kozlowski
2026-02-28 14:17 ` [PATCH v3 3/4] dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XP Pengyu Luo
2026-03-01 11:46 ` Krzysztof Kozlowski
2026-02-28 14:17 ` Pengyu Luo [this message]
2026-02-28 14:28 ` [PATCH v3 4/4] arm64: dts: qcom: sc8280xp: Add dsi nodes " Dmitry Baryshkov
2026-03-02 11:02 ` Konrad Dybcio
2026-03-07 10:24 ` kernel test robot
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