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Mon, 02 Mar 2026 19:02:02 +0000 (GMT) Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14879.it.hpe.com (Postfix) with ESMTPS id 1B64DB4288; Mon, 2 Mar 2026 19:02:02 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id A3E2481AD37; Mon, 2 Mar 2026 19:02:01 +0000 (UTC) From: nick.hawkins@hpe.com To: ulf.hansson@linaro.org, adrian.hunter@intel.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: jszhang@kernel.org, nick.hawkins@hpe.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 0/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support Date: Mon, 2 Mar 2026 13:01:39 -0600 Message-Id: <20260302190141.1481298-1-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDE0OCBTYWx0ZWRfXw7b5Fjl/ttQT 7L3Ejl6lJrZz8x8JZuZmCeVQs3hxJ01s7gG6/D+tElqZzCerR/Pf15vu9b02ScE04f2coh2+wcs NY6l84wK+Rl3w1h8cc07/Ow0LkNR9TioODY6HALQLQZ8QizdZxuZ0dcqttPRc/htZNafMHZsraM W8OcZq75R9FcuB4HKZUKwQYtOtcP1Urk+0f3SpLcNhV1B3wy9a7DcBqfP+gGHERkzRJagHSR+vm hfkv/FUnCpFAdvyeIs+McQxzz6BNC2SPT8vButu4PzTeg/D3kygpq/XMemNlodxwTGiPCBvW1n4 0KNr2PhSTgZd+hPmhqfS7tY0Za9nPqfVFqap5QIU4yomFfEY943NqbJ/ftW2qL+mZcErnL5syNM L5WwxbSp6yIa/tPiAe3lEHpW1rTkFgvmcqOze+f0PYoVlbswvWbUoetF/mQmKVzUxkOnqcRgmzx UyQH3y67GrZn3FM+N4A== X-Authority-Analysis: v=2.4 cv=NPvYOk6g c=1 sm=1 tr=0 ts=69a5deaa cx=c_pps a=5jkVtQsCUlC8zk5UhkBgHg==:117 a=5jkVtQsCUlC8zk5UhkBgHg==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gQcMVamqm3wCPoSYhaRC:22 a=_ZmgHqWwjZUDpi_pur5s:22 a=MvuuwTCpAAAA:8 a=7CkxuHwdN_sW70-Q_JcA:9 X-Proofpoint-GUID: 57KN_tZxTOhSlBSYQN7WH7a3nCchF9Xl X-Proofpoint-ORIG-GUID: 57KN_tZxTOhSlBSYQN7WH7a3nCchF9Xl X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_04,2026-03-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 clxscore=1011 malwarescore=0 adultscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603020148 From: Nick Hawkins The HPE GSC is an ARM64 (Cortex-A53) BMC SoC used on HPE ProLiant servers. Its eMMC controller is based on the DesignWare Cores MSHC IP (snps,dwcmshc) but requires a small set of platform-specific quirks that cannot be expressed through the existing generic dwcmshc code paths. This series adds support for the 'hpe,gsc-dwcmshc' compatible: Patch 1 extends the snps,dwcmshc-sdhci.yaml binding to document the new compatible and the mandatory second reg entry for MSHCCS (DTS reg[1]). The HPE GSC exposes only a single 'core' clock, so the clocks/clock-names properties are constrained to maxItems: 1 for this compatible. Patch 2 adds the HPE-specific driver code in sdhci-of-dwcmshc.c: * dwcmshc_hpe_set_clock(): SDHCI_CLOCK_CONTROL.freq_sel is wired to a clock mux on the GSC SoC, not a divider. When running at 200 MHz (HS200) freq_sel must be forced to 1 to select the correct high-frequency source. * dwcmshc_hpe_vendor_specific(): disables the command-conflict check and programs ATCTRL = 0x021f0005 for reliable HS200 signal integrity on the GSC board topology (auto-tuning enable, centre-phase mode, tune-clock-stop, pre/post-change delays = 3). * dwcmshc_hpe_reset(): calls sdhci_reset(), re-applies vendor config, and unconditionally re-sets CARD_IS_EMMC. The controller clears this bit on every reset; leaving it clear causes card-detect misidentification on the eMMC-only slot. * dwcmshc_hpe_set_uhs_signaling(): mirrors upstream dwcmshc_set_uhs_signaling() but always asserts CARD_IS_EMMC. * dwcmshc_hpe_gsc_init(): maps MSHCCS from DTS reg[1], sets SCGSyncDis (BIT(18)) to allow the HS200 RX delay lines to settle while the card clock is stopped, enables SDHCI v4 mode. * sdhci_dwcmshc_hpe_gsc_pdata sets SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (base clock not in capabilities) and SDHCI_QUIRK2_PRESET_VALUE_BROKEN (preset-value registers not populated in GSC ROM). All new symbols are exclusively selected by the 'hpe,gsc-dwcmshc' OF match entry. No existing platform (Rockchip, T-Head, sg2042, Sophgo, etc.) has any code path change. Note: the DTS node for 'hpe,gsc-dwcmshc' will be submitted separately as part of the HPE GSC base platform series (arch/arm64/boot/dts/hpe/). Changes since RFC: first formal submission. Nick Hawkins (2): dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 43 ++++- drivers/mmc/host/sdhci-of-dwcmshc.c | 166 ++++++++++++++++++ 2 files changed, 208 insertions(+), 1 deletion(-) base-commit: 7dff99b354601dd01829e1511711846e04340a69 -- 2.34.1