[PATCH 1/2] spi: dt-bindings: mpfs-spi: permit resets

[Conor Dooley <conor@kernel.org>]

From: Conor Dooley <conor.dooley@microchip.com>

CoreSPI, CoreQSPI and the hardened versions of them on mpfs and
pic64gx have a reset pin. For the first two, usually this is wired to
a common fabric reset not managed by software and for the latter two
the platform firmware takes them out of reset on first-party boards
(or those using modified versions of the vendor firmware), but not all
boards may take this approach. Permit providing a reset in devicetree
for Linux, or other devicetree-consuming software, to use.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Mark Brown <broonie@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: linux-spi@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index 636338d24bdfb..b7d8acc924be4 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -41,6 +41,9 @@ properties:
   clocks:
     maxItems: 1
 
+  resets:
+    maxItems: 1
+
   microchip,apb-datawidth:
     description: APB bus data width in bits.
     $ref: /schemas/types.yaml#/definitions/uint32
-- 
2.51.0