From: Akhil R <akhilrajeev@nvidia.com>
To: <krzk@kernel.org>
Cc: <Frank.Li@kernel.org>, <akhilrajeev@nvidia.com>,
<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
<dmaengine@vger.kernel.org>, <jonathanh@nvidia.com>,
<krzk+dt@kernel.org>, <ldewangan@nvidia.com>,
<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<p.zabel@pengutronix.de>, <robh@kernel.org>,
<thierry.reding@kernel.org>, <vkoul@kernel.org>
Subject: Re: [PATCH v2 1/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property
Date: Tue, 3 Mar 2026 14:10:05 +0530 [thread overview]
Message-ID: <20260303084005.57114-1-akhilrajeev@nvidia.com> (raw)
In-Reply-To: <20260303-famous-fearless-asp-1240cb@quoll>
On Tue, 3 Mar 2026 07:39:58 +0100 Krzysztof Kozlowski wrote:
> On Mon, Mar 02, 2026 at 06:02:31PM +0530, Akhil R wrote:
>> Add iommu-map property to specify separate stream IDs for each DMA
>> channel. This enables each channel to be in its own IOMMU domain,
>> keeping memory isolated from other devices sharing the same DMA
>> controller.
>>
>> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
>> ---
>> .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
>> index 0dabe9bbb219..1e7b5ddd4658 100644
>> --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
>> @@ -14,6 +14,7 @@ description: |
>> maintainers:
>> - Jon Hunter <jonathanh@nvidia.com>
>> - Rajesh Gumasta <rgumasta@nvidia.com>
>> + - Akhil R <akhilrajeev@nvidia.com>
>>
>> allOf:
>> - $ref: dma-controller.yaml#
>> @@ -51,6 +52,10 @@ properties:
>> iommus:
>> maxItems: 1
>>
>> + iommu-map:
>> + minItems: 1
>> + maxItems: 32
>
> Why is this flexible? If it is, means usually items are distinctive, so
> I would expect defining/listing them. If they are not distinctive,
> commit msg is incorrect. If the list is as simple as 1-to-1 channel
> mapping, just add it in the description how they are ordered.
Yes, it is a 1-to-1 channel mapping to an IOMMU ID. The intent of making
it flexible is to allow non-consecutive IOMMU ID assignments as well.
This is particularly needed in virtualised environments where the
hypervisor may reserve certain stream IDs, and the guest VM can map only
the permitted ones. Shall I add a description here mentioning this
use-case?
>
>> +
>> dma-coherent: true
>>
>> dma-channel-mask:
>> --
>> 2.50.1
>
next prev parent reply other threads:[~2026-03-03 8:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 12:32 [PATCH v2 0/9] Add GPCDMA support in Tegra264 Akhil R
2026-03-02 12:32 ` [PATCH v2 1/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property Akhil R
2026-03-03 6:39 ` Krzysztof Kozlowski
2026-03-03 8:40 ` Akhil R [this message]
2026-03-03 8:57 ` Krzysztof Kozlowski
2026-03-03 13:09 ` Jon Hunter
2026-03-03 17:14 ` Akhil R
2026-03-03 17:34 ` Jon Hunter
2026-03-04 10:37 ` Akhil R
2026-03-04 11:10 ` Jon Hunter
2026-03-10 4:44 ` Akhil R
2026-03-10 9:47 ` Jon Hunter
2026-03-02 12:32 ` [PATCH v2 2/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional Akhil R
2026-03-02 20:31 ` Frank Li
2026-03-03 13:27 ` Jon Hunter
2026-03-02 12:32 ` [PATCH v2 3/9] dmaengine: tegra: Make reset control optional Akhil R
2026-03-02 20:31 ` Frank Li
2026-03-02 12:32 ` [PATCH v2 4/9] dmaengine: tegra: Use struct for register offsets Akhil R
2026-03-02 12:32 ` [PATCH v2 5/9] dmaengine: tegra: Support address width > 39 bits Akhil R
2026-03-02 21:14 ` Frank Li
2026-03-02 12:32 ` [PATCH v2 6/9] dmaengine: tegra: Use managed DMA controller registration Akhil R
2026-03-02 12:32 ` [PATCH v2 7/9] dmaengine: tegra: Use iommu-map for stream ID Akhil R
2026-03-02 12:32 ` [PATCH v2 8/9] dmaengine: tegra: Add Tegra264 support Akhil R
2026-03-02 12:32 ` [PATCH v2 9/9] arm64: tegra: Add iommu-map and enable GPCDMA in Tegra264 Akhil R
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