* [PATCH v2 0/3] SDM670 Basic SoC thermal zones
@ 2026-03-04 1:45 Richard Acayan
2026-03-04 1:45 ` [PATCH v2 1/3] dt-bindings: thermal: tsens: add SDM670 compatible Richard Acayan
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Richard Acayan @ 2026-03-04 1:45 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Amit Kucheria,
Thara Gopinath, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-pm, devicetree
Cc: Richard Acayan
This adds support for the thermal sensor, for thermal-based CPU
throttling via LMh, and for thermal zones.
Changes since v1 (https://lore.kernel.org/r/20260210021607.12576-1-mailingradian@gmail.com):
- add review tag from Krzysztof (1/3)
- replace CPU thermal zones with lmh (2/3, 3/3)
Richard Acayan (3):
dt-bindings: thermal: tsens: add SDM670 compatible
dt-bindings: thermal: lmh: Add SDM670 compatible
arm64: dts: qcom: sdm670: add thermal zones and thermal devices
.../devicetree/bindings/thermal/qcom-lmh.yaml | 3 +
.../bindings/thermal/qcom-tsens.yaml | 1 +
arch/arm64/boot/dts/qcom/sdm670.dtsi | 474 ++++++++++++++++++
3 files changed, 478 insertions(+)
--
2.53.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] dt-bindings: thermal: tsens: add SDM670 compatible
2026-03-04 1:45 [PATCH v2 0/3] SDM670 Basic SoC thermal zones Richard Acayan
@ 2026-03-04 1:45 ` Richard Acayan
2026-03-04 1:45 ` [PATCH v2 2/3] dt-bindings: thermal: lmh: Add " Richard Acayan
2026-03-04 1:45 ` [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Richard Acayan
2 siblings, 0 replies; 6+ messages in thread
From: Richard Acayan @ 2026-03-04 1:45 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Amit Kucheria,
Thara Gopinath, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-pm, devicetree
Cc: Richard Acayan
Add the compatible for the thermal sensors on the SDM670.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 3c5256b0cd9f..6c84f22ae322 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -71,6 +71,7 @@ properties:
- qcom,sc8180x-tsens
- qcom,sc8280xp-tsens
- qcom,sdm630-tsens
+ - qcom,sdm670-tsens
- qcom,sdm845-tsens
- qcom,sm6115-tsens
- qcom,sm6350-tsens
--
2.53.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] dt-bindings: thermal: lmh: Add SDM670 compatible
2026-03-04 1:45 [PATCH v2 0/3] SDM670 Basic SoC thermal zones Richard Acayan
2026-03-04 1:45 ` [PATCH v2 1/3] dt-bindings: thermal: tsens: add SDM670 compatible Richard Acayan
@ 2026-03-04 1:45 ` Richard Acayan
2026-03-04 1:45 ` [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Richard Acayan
2 siblings, 0 replies; 6+ messages in thread
From: Richard Acayan @ 2026-03-04 1:45 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Amit Kucheria,
Thara Gopinath, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-pm, devicetree
Cc: Richard Acayan
Document the SDM670 LMh.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
Documentation/devicetree/bindings/thermal/qcom-lmh.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
index 1175bb358382..ce72347e29d1 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
@@ -22,6 +22,9 @@ properties:
- qcom,sc8180x-lmh
- qcom,sdm845-lmh
- qcom,sm8150-lmh
+ - items:
+ - const: qcom,sdm670-lmh
+ - const: qcom,sdm845-lmh
- items:
- const: qcom,qcm2290-lmh
- const: qcom,sm8150-lmh
--
2.53.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
2026-03-04 1:45 [PATCH v2 0/3] SDM670 Basic SoC thermal zones Richard Acayan
2026-03-04 1:45 ` [PATCH v2 1/3] dt-bindings: thermal: tsens: add SDM670 compatible Richard Acayan
2026-03-04 1:45 ` [PATCH v2 2/3] dt-bindings: thermal: lmh: Add " Richard Acayan
@ 2026-03-04 1:45 ` Richard Acayan
2026-03-04 1:55 ` Dmitry Baryshkov
2 siblings, 1 reply; 6+ messages in thread
From: Richard Acayan @ 2026-03-04 1:45 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Amit Kucheria,
Thara Gopinath, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-pm, devicetree
Cc: Richard Acayan
Add thermal zones to safeguard from overheating to high temperatures,
along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
The temperatures are very high, but should still be safeguard for
devices that do not specify their own thermal zones.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 474 +++++++++++++++++++++++++++
1 file changed, 474 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index f115bc6e64f3..3a55b24ff93b 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -20,6 +20,7 @@
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -62,6 +63,7 @@ cpu0: cpu@0 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
@@ -89,6 +91,7 @@ cpu1: cpu@100 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
@@ -111,6 +114,7 @@ cpu2: cpu@200 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
@@ -133,6 +137,7 @@ cpu3: cpu@300 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
@@ -155,6 +160,7 @@ cpu4: cpu@400 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_400>;
l2_400: l2-cache {
compatible = "cache";
@@ -177,6 +183,7 @@ cpu5: cpu@500 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_500>;
l2_500: l2-cache {
compatible = "cache";
@@ -199,6 +206,7 @@ cpu6: cpu@600 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_600>;
l2_600: l2-cache {
compatible = "cache";
@@ -221,6 +229,7 @@ cpu7: cpu@700 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_700>;
l2_700: l2-cache {
compatible = "cache";
@@ -1408,6 +1417,8 @@ gpu: gpu@5000000 {
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
+
status = "disabled";
gpu_zap_shader: zap-shader {
@@ -2100,6 +2111,28 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
};
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sdm670-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>,
+ <0 0x0c222000 0 0x4>;
+ interrupts-extended = <&pdc 26 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 28 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ #qcom,sensors = <13>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sdm670-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>,
+ <0 0x0c223000 0 0x4>;
+ interrupts-extended = <&pdc 27 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 29 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ #qcom,sensors = <8>;
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
@@ -2289,5 +2322,446 @@ cpufreq_hw: cpufreq@17d43000 {
#freq-domain-cells = <1>;
};
+
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh";
+ reg = <0 0x17d70800 0 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu6>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh";
+ reg = <0 0x17d78800 0 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu0>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu0_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu1_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu2_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu2_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu3_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu3_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cluster0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cluster0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cluster0_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cluster1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cluster1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cluster1_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu4_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu4_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu5_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu5_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu6_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu6_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cpu7_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ gpu0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ gpu0_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ gpu1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ gpu1_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ q6-modem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ q6_modem_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ mem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ cooling-maps {
+ map0 {
+ trip = <&mem_alert0>;
+ cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ mem_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ mem_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ wlan-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ wlan_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ q6-hvx-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ q6_hvx_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ camera_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ video_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ modem_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
};
};
--
2.53.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
2026-03-04 1:45 ` [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Richard Acayan
@ 2026-03-04 1:55 ` Dmitry Baryshkov
2026-03-04 18:38 ` Richard Acayan
0 siblings, 1 reply; 6+ messages in thread
From: Dmitry Baryshkov @ 2026-03-04 1:55 UTC (permalink / raw)
To: Richard Acayan
Cc: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Amit Kucheria,
Thara Gopinath, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-pm, devicetree
On Tue, Mar 03, 2026 at 08:45:30PM -0500, Richard Acayan wrote:
> Add thermal zones to safeguard from overheating to high temperatures,
> along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
> The temperatures are very high, but should still be safeguard for
> devices that do not specify their own thermal zones.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 474 +++++++++++++++++++++++++++
> 1 file changed, 474 insertions(+)
>
> +
> + mem-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens1 2>;
> +
> + cooling-maps {
> + map0 {
> + trip = <&mem_alert0>;
> + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
Why is it only cpu6 & 7? Note, SDM845 doesn't have any cooling maps for
mem-thermal.
> + };
> + };
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
2026-03-04 1:55 ` Dmitry Baryshkov
@ 2026-03-04 18:38 ` Richard Acayan
0 siblings, 0 replies; 6+ messages in thread
From: Richard Acayan @ 2026-03-04 18:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Amit Kucheria,
Thara Gopinath, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-pm, devicetree
On Wed, Mar 04, 2026 at 03:55:21AM +0200, Dmitry Baryshkov wrote:
> On Tue, Mar 03, 2026 at 08:45:30PM -0500, Richard Acayan wrote:
> > Add thermal zones to safeguard from overheating to high temperatures,
> > along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
> > The temperatures are very high, but should still be safeguard for
> > devices that do not specify their own thermal zones.
> >
> > Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> > ---
> > arch/arm64/boot/dts/qcom/sdm670.dtsi | 474 +++++++++++++++++++++++++++
> > 1 file changed, 474 insertions(+)
> >
> > +
> > + mem-thermal {
> > + polling-delay-passive = <250>;
> > + polling-delay = <1000>;
> > +
> > + thermal-sensors = <&tsens1 2>;
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&mem_alert0>;
> > + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>
> Why is it only cpu6 & 7?
They are supposed to have the highest available power consumption
(implying highest TDP).
> Note, SDM845 doesn't have any cooling maps for
> mem-thermal.
Makes sense, the cooling can be removed.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-03-04 18:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-04 1:45 [PATCH v2 0/3] SDM670 Basic SoC thermal zones Richard Acayan
2026-03-04 1:45 ` [PATCH v2 1/3] dt-bindings: thermal: tsens: add SDM670 compatible Richard Acayan
2026-03-04 1:45 ` [PATCH v2 2/3] dt-bindings: thermal: lmh: Add " Richard Acayan
2026-03-04 1:45 ` [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Richard Acayan
2026-03-04 1:55 ` Dmitry Baryshkov
2026-03-04 18:38 ` Richard Acayan
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