From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB8803CEB9B; Tue, 28 Apr 2026 07:27:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777361245; cv=none; b=VE/5k24pujkfHvskkH14+f7A8MQJjxcR8Kc+HkI4rUeAHRnr8JrV17mD3WAN1csvlbuGQJxoO4EU11Ut3P9mn/sFfaDZwBrKmCGVfHmckoovZLEzVBUQa+L8ILVgFmmCjpTVsQtRcLLfonKsviRyqn5n68PEJZvcNq3+3HfAL68= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777361245; c=relaxed/simple; bh=canMdQn5hfFwDUTk6yP+9Z2IYMwny/ISt+Qq1ILrQhs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VHY5V+2G2t5JykswZODxrDddmvx9+r0ImSllUGxJUW0JMPCVRfW/BO9ww3SIewnEOGQkzDEjC7NPiN4LiKK4VVXAdFYei3ivJ6mY6TefYHo008ecfVKpicpjIV/Y7CY3bA6JODmz81KDM8isn+5DFc7lHENEFRQBChb7FRc0IRM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SHo8Oq2L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SHo8Oq2L" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8FC59C2BCB5; Tue, 28 Apr 2026 07:27:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777361245; bh=canMdQn5hfFwDUTk6yP+9Z2IYMwny/ISt+Qq1ILrQhs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SHo8Oq2LlkpnfBOGmQUn5z511lzrl9DUoclhLBQSGJOLwSiA+MZ1CaGF0RUCaphAx 2kFJwGPFkAqZhB0AreEVgCgXNmgMznKB0yEpZUZCCGauzqK2pjD8FA52xy7KPdldSz 7LwIQ0jqRJ4AzJmTR5HJVWeGXL5wufH/8rc1W3Dk0e/06qvLjYAaCpdx2dys8oapTM a/ZOjKahwxHzVjIY6ENYMW6davPtTADy4qFK4Ijo99WJWhfgJYGJ/WjELLr0IsyOYw 1bcpHPYxXoG5idNPNtOywRK/cflDvh4UvSUJx0rfrBh232ePSzOLCmCk6pqkTht7St 0KZD1xhmjB3iw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80BBAFF886F; Tue, 28 Apr 2026 07:27:25 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 28 Apr 2026 09:27:24 +0200 Subject: [PATCH v5 2/2] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260305-rk3588-csi2rx-v5-2-3b7061d043ea@collabora.com> References: <20260305-rk3588-csi2rx-v5-0-3b7061d043ea@collabora.com> In-Reply-To: <20260305-rk3588-csi2rx-v5-0-3b7061d043ea@collabora.com> To: Mauro Carvalho Chehab , Sakari Ailus , Laurent Pinchart , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Collabora Kernel Team Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777361244; l=2502; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=QDfqcbJrT0FfjmyC+y7b4XMGt2ND2RSPd6Nzsjmcagk=; b=tzBpqb+biprATyCYOADHv3ffINsOlbTfx79xtKUveu9fGstM/74z31mom4wpaqSAype1f5mws gFs2EQESeXADtvPYFfeKGLkDG5k3lnfQTM18E7YwrRWf3iXrVi9y5Gi X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features six MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 (not supported) - MIPI1: connected to MIPI DCPHY1 (not supported) - MIPI2: connected to MIPI DPHY0 - MIPI3: connected to MIPI DPHY0-1 (not supported) - MIPI4: connected to MIPI DPHY1 - MIPI5: connected to MIPI DPHY1-1 (not supported) As the MIPI DCPHYs as well as the split DPHY mode of the DPHYs are not yet supported, add only the device tree nodes for the MIPI2 and MIPI4 units. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4fb8888c281c..4d80e5e1f033 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1430,6 +1430,58 @@ av1d: video-codec@fdc70000 { resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; }; + csi2: csi@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd30000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_2>; + phys = <&csi_dphy0>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_in: port@0 { + reg = <0>; + }; + + csi2_out: port@1 { + reg = <1>; + }; + }; + }; + + csi4: csi@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd50000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_4>; + phys = <&csi_dphy1>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi4_in: port@0 { + reg = <0>; + }; + + csi4_out: port@1 { + reg = <1>; + }; + }; + }; + vop: vop@fdd90000 { compatible = "rockchip,rk3588-vop"; reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; -- 2.39.5