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[93.34.88.122]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-439dae2ba66sm4743436f8f.20.2026.03.06.11.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 11:02:05 -0800 (PST) From: Christian Marangi To: Christian Marangi , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Conor Dooley Subject: [PATCH v6 2/4] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY Date: Fri, 6 Mar 2026 20:01:51 +0100 Message-ID: <20260306190156.22297-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260306190156.22297-1-ansuelsmth@gmail.com> References: <20260306190156.22297-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add documentation for Airoha AN7581 USB PHY that describe the USB PHY for the USB controller. Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is always supported. The USB 3.0 mode is optional and depends on the Serdes mode currently configured on the system for the relevant USB port. To correctly calibrate, the USB 2.0 port require correct value in "airoha,usb2-monitor-clk-sel" property. Both the 2 USB 2.0 port permit selecting one of the 4 monitor clock for calibration (internal clock not exposed to the system) but each port have only one of the 4 actually connected in HW hence the correct value needs to be specified in DT based on board and the physical port. Normally it's monitor clock 1 for USB1 and monitor clock 2 for USB2. To correctly setup the Serdes mode attached to the USB 3.0 mode, the "airoha,usb3-serdes" property is required. This can be either AIROHA_SCU_SERDES_USB1 or AIROHA_SCU_SERDES_USB2 and is used to identify what modes support the PHY and what register to use to setup the requested mode. The first USB port on the SoC can be both used for USB 3.0 operation or Ethernet (HSGMII). The second USB port on the SoC can be both used for USB 3.0 operation or for an additional PCIe line. Signed-off-by: Christian Marangi Reviewed-by: Conor Dooley --- .../bindings/phy/airoha,an7581-usb-phy.yaml | 71 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml new file mode 100644 index 000000000000..ec467fb7f971 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7581-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7581 SoC USB PHY + +maintainers: + - Christian Marangi + +description: > + The Airoha AN7581 SoC USB PHY describes the USB PHY for the USB controller. + + Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is + always supported. The USB 3.0 mode is optional and depends on the Serdes + mode currently configured on the system for the relevant USB port. + + The first USB port on the SoC can be both used for USB 3.0 operation or + Ethernet (HSGMII). + The second USB port on the SoC can be both used for USB 3.0 operation or + for an additional PCIe line. + +properties: + compatible: + const: airoha,an7581-usb-phy + + reg: + maxItems: 1 + + airoha,usb2-monitor-clk-sel: + description: Describe what oscillator across the available 4 + should be selected for USB 2.0 Slew Rate calibration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + airoha,usb3-serdes: + description: Describe what Serdes line is attached to the USB 3.0 port. + Can be either AIROHA_SCU_SERDES_USB1 or AIROHA_SCU_SERDES_USB2 as + defined in dt-bindings/soc/airoha,scu-ssr.h + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + '#phy-cells': + description: The cell contains the mode, PHY_TYPE_USB2 or PHY_TYPE_USB3, + as defined in dt-bindings/phy/phy.h. + const: 1 + +required: + - compatible + - reg + - airoha,usb2-monitor-clk-sel + - airoha,usb3-serdes + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + + phy@1fac0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x1fac0000 0x10000>; + + airoha,usb2-monitor-clk-sel = <1>; + airoha,usb3-serdes = ; + + #phy-cells = <1>; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index 364f0bec8748..d75f59118a9a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -779,6 +779,12 @@ S: Maintained F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml F: drivers/spi/spi-airoha-snfi.c +AIROHA USB PHY DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml + AIRSPY MEDIA DRIVER L: linux-media@vger.kernel.org S: Orphan -- 2.51.0