Re: [PATCH 3/3] iio: adc: ad4130: add new supported parts

[Jonathan Cameron <jic23@kernel.org>]

On Sat, 28 Feb 2026 09:39:04 -0300
Jonathan Santos <Jonathan.Santos@analog.com> wrote:

> Add support for AD4129-4/8, AD4130-4, and AD4131-4/8 variants.
> 
> The AD4129 series supports the same FIFO interface as the AD4130 but with
> reduced resolution (16-bit). The AD4131 series lacks FIFO support, so
> triggered buffer functionality is introduced.
> 
> The 4-channel variants feature fewer analog inputs, GPIOs, and sparse pin
> mappings for VBIAS, analog inputs, and excitation currents. The driver now
> handles these differences with chip-specific configurations, including pin
> mappings and GPIO counts.
> 
> Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
A couple of things inline.

> +static irqreturn_t ad4130_trigger_handler(int irq, void *p)
> +{
> +	struct iio_poll_func *pf = p;
> +	struct iio_dev *indio_dev = pf->indio_dev;
> +	struct ad4130_state *st = iio_priv(indio_dev);
> +	unsigned int data_reg_size = ad4130_data_reg_size(st);
> +	unsigned int num_en_chn = bitmap_weight(indio_dev->active_scan_mask,
> +						iio_get_masklength(indio_dev));
> +	struct spi_transfer xfer = {
> +		.rx_buf = st->scan.channels,
> +		.len = data_reg_size * num_en_chn,
> +	};
> +	int ret;
> +
> +	ret = spi_sync_transfer(st->spi, &xfer, 1);
> +	if (ret < 0)
> +		goto err_unlock;
> +
> +	iio_push_to_buffers_with_timestamp(indio_dev, &st->scan,
> +					   iio_get_time_ns(indio_dev));
> +
> +err_unlock:

Needs a rename seeing as no locks involved.

> +	iio_trigger_notify_done(indio_dev->trig);
>  
>  	return IRQ_HANDLED;
>  }
> @@ -1300,12 +1416,77 @@ static const struct iio_info ad4130_info = {
>  	.debugfs_reg_access = ad4130_reg_access,
>  };

> @@ -2100,34 +2383,46 @@ static int ad4130_probe(struct spi_device *spi)
>  	if (ret)
>  		return dev_err_probe(dev, ret, "Failed to request irq\n");
>  
> -	/*
> -	 * When the chip enters FIFO mode, IRQ polarity is inverted.
> -	 * When the chip exits FIFO mode, IRQ polarity returns to normal.
> -	 * See datasheet pages: 65, FIFO Watermark Interrupt section,
> -	 * and 71, Bit Descriptions for STATUS Register, RDYB.
> -	 * Cache the normal and inverted IRQ triggers to set them when
> -	 * entering and exiting FIFO mode.
> -	 */
> -	st->irq_trigger = irq_get_trigger_type(spi->irq);
> -	if (st->irq_trigger & IRQF_TRIGGER_RISING)
> -		st->inv_irq_trigger = IRQF_TRIGGER_FALLING;
> -	else if (st->irq_trigger & IRQF_TRIGGER_FALLING)
> -		st->inv_irq_trigger = IRQF_TRIGGER_RISING;
> -	else
> -		return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n",
> -				     st->irq_trigger);
> +	if (st->chip_info->has_fifo) {
> +		/*
> +		 * When the chip enters FIFO mode, IRQ polarity is inverted.
> +		 * When the chip exits FIFO mode, IRQ polarity returns to normal.
> +		 * See datasheet pages: 65, FIFO Watermark Interrupt section,
> +		 * and 71, Bit Descriptions for STATUS Register, RDYB.
> +		 * Cache the normal and inverted IRQ triggers to set them when
> +		 * entering and exiting FIFO mode.

That's special.   The binding doc needs an update to say which state we are
expecting an irq description for.  Obviously not a result of this
series but nice to add that none the less!

> +		 */
> +		st->irq_trigger = irq_get_trigger_type(spi->irq);
> +		if (st->irq_trigger & IRQF_TRIGGER_RISING)
> +			st->inv_irq_trigger = IRQF_TRIGGER_FALLING;
> +		else if (st->irq_trigger & IRQF_TRIGGER_FALLING)
> +			st->inv_irq_trigger = IRQF_TRIGGER_RISING;
> +		else
> +			return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n",
> +					     st->irq_trigger);
> +	}
>  
>  	return devm_iio_device_register(dev, indio_dev);
>  }