[RFC PATCH 1/1] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

[Nicholas Piggin <npiggin@gmail.com>]

Extend the binding to cover details specific to the Tenstorrent RISC-V
IOMMU. In particular, a second register range is added which contains
M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register
range and are compatible with "riscv,iommu" so the Linux driver does not
notice any difference, but the binding will be used by OpenSBI and
potentially other M-mode software.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Hi,

This binding will be used in a Tenstorrent SoC platform device-tree that
we plan to get upstream some time, but I wanted to ask for any comments
here before the OpenSBI platform code that uses it is merged.

Thanks,
Nick
---
 .../bindings/iommu/riscv,iommu.yaml           | 67 +++++++++++++++++--
 1 file changed, 60 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
index d4838c3b3741..3c680e53af64 100644
--- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
@@ -32,22 +32,40 @@ properties:
   # should be specified along with 'reg' property providing MMIO location.
   compatible:
     oneOf:
-      - items:
+      - description: Platform (non-PCIe) IOMMU implementations
+        items:
           - enum:
               - qemu,riscv-iommu
           - const: riscv,iommu
-      - items:
+      - description: PCIe IOMMU implementations
+        items:
           - enum:
               - pci1efd,edf1
           - const: riscv,pci-iommu
+      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
+        items:
+          - enum:
+              - tenstorrent,riscv-iommu
+          - const: riscv,iommu
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
     description:
-      For non-PCI devices this represents base address and size of for the
-      IOMMU memory mapped registers interface.
-      For PCI IOMMU hardware implementation this should represent an address
-      of the IOMMU, as defined in the PCI Bus Binding reference.
+      For non-PCI devices the first item represents base address and size of
+      for the IOMMU memory mapped registers interface.
+      For PCI IOMMU hardware implementation the first item should represent
+      an address of the IOMMU, as defined in the PCI Bus Binding reference.
+
+  reg-names:
+    items:
+      - const: base
+        description:
+          Minimum 4KiB region beginning with RISC-V IOMMU MMRs.
+      - const: machine
+        description:
+          Optional region containing platform specific MMRs for machine-mode
+          configuration, for example PMA and PMP registers.
 
   '#iommu-cells':
     const: 1
@@ -75,6 +93,31 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.
+        reg-names:
+          items:
+            - const: base
+            - const: machine
+              description:
+                Region containing platform specific MMRs for machine-mode
+                configuration, such as PMA and PMP registers.
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
 examples:
   - |+
     /* Example 1 (IOMMU device with wired interrupts) */
@@ -145,3 +188,13 @@ examples:
             };
         };
     };
+
+  - |+
+    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
+    iommu5: iommu@d2020000 {
+        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
+        reg = <0x0 0xd2020000 0x0 0x10000 0x0 0xaa000000 0x0 0x10000>;
+        reg-names = "base", "machine";
+        msi-parent = <&imsics_smode>;
+        #iommu-cells = <1>;
+    };
-- 
2.51.0