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From: Akhil R <akhilrajeev@nvidia.com>
To: <jonathanh@nvidia.com>
Cc: <Frank.Li@kernel.org>, <akhilrajeev@nvidia.com>,
	<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
	<dmaengine@vger.kernel.org>, <krzk+dt@kernel.org>,
	<krzk@kernel.org>, <ldewangan@nvidia.com>,
	<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<p.zabel@pengutronix.de>, <robh@kernel.org>,
	<thierry.reding@kernel.org>, <vkoul@kernel.org>
Subject: Re: [PATCH v2 1/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property
Date: Tue, 10 Mar 2026 10:14:25 +0530	[thread overview]
Message-ID: <20260310044426.53519-1-akhilrajeev@nvidia.com> (raw)
In-Reply-To: <9740033b-0fa4-46c6-9628-f4c3ba1cceae@nvidia.com>

Hi Krzysztof and Jon,

On Wed, 4 Mar 2026 11:10:55 +0000, Jon Hunter wrote:
> On 04/03/2026 10:37, Akhil R wrote:
>> On Tue, 3 Mar 2026 17:34:00 +0000, Jon Hunter wrote:
>>> On 03/03/2026 17:14, Akhil R wrote:
>>>> On Tue, 3 Mar 2026 13:09:00 +0000, Jon Hunter wrote:
>>>>> On 03/03/2026 08:40, Akhil R wrote:
>>>>>
>>>>> ...
>>>>>
>>>>>>> Why is this flexible? If it is, means usually items are distinctive, so
>>>>>>> I would expect defining/listing them. If they are not distinctive,
>>>>>>> commit msg is incorrect. If the list is as simple as 1-to-1 channel
>>>>>>> mapping, just add it in the description how they are ordered.
>>>>>>
>>>>>> Yes, it is a 1-to-1 channel mapping to an IOMMU ID. The intent of making
>>>>>> it flexible is to allow non-consecutive IOMMU ID assignments as well.
>>>>>> This is particularly needed in virtualised environments where the
>>>>>> hypervisor may reserve certain stream IDs, and the guest VM can map only
>>>>>> the permitted ones. Shall I add a description here mentioning this
>>>>>> use-case?
>>>>>
>>>>> Isn't this already handled by the 'dma-channel-mask' property? The
>>>>> driver will skip over any channels that are not in specified by the mask.
>>>>
>>>> dma-channel-mask would not help if a channel is exposed, and the
>>>> corresponding IOMMU ID is not exposed. For instance say channel 15 is
>>> available for a VM, but not the stream ID 0x80f.
>>>
>>> Is that a valid configuration? Above we said it is a 1-to-1 mapping
>>> which would imply the mapping is always constant. Ie. same channels maps
>>> to name SID. Is that not the case?
>> 
>> I think the hypervisor configuration can determinte which stream IDs
>> are assigned to each VM, so the mapping can vary across platforms.
>> By 1-to-1, I meant that each channel maps to one IOMMU ID, but the
>> specific IDs themselves may not be fixed. If we prefer a constant
>> mapping instead, we could document that only IDs in the range 0x801 to
>> 0x81f should be allocated to a Linux VM. Happy to go either way. Let me
>> know your thoughts.
> 
> I guess I don't know what flexibility we need here. But the more 
> flexible, the more complex the binding and so if we need that 
> flexibility then you will need to look at how Qualcomm solved this for 
> their 'iris video codec' as Krzysztof mentioned.

Looking at the qcom,sm8750-camss.yaml, each iommus entry is describing a
functionally distinct hardware block like IPE, JPEG, etc. Here for
GPCDMA the channels and the stream IDs are identical in hardware and there
is nothing functionally unique about any individual channel to describe.

If the channels and stream IDs are consecutive, as Frank mentioned in
the previous version, we would need only one iommu-map entry for all
the channels. In a virtualized system the hypervisor may assign
non-consecutive stream IDs, or a scattered channel mask. That would
require multiple entries.

I will document this in the description. Please let me know if it sounds
good or if you have any suggestions.

Regards,
Akhil

  reply	other threads:[~2026-03-10  4:44 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-02 12:32 [PATCH v2 0/9] Add GPCDMA support in Tegra264 Akhil R
2026-03-02 12:32 ` [PATCH v2 1/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property Akhil R
2026-03-03  6:39   ` Krzysztof Kozlowski
2026-03-03  8:40     ` Akhil R
2026-03-03  8:57       ` Krzysztof Kozlowski
2026-03-03 13:09       ` Jon Hunter
2026-03-03 17:14         ` Akhil R
2026-03-03 17:34           ` Jon Hunter
2026-03-04 10:37             ` Akhil R
2026-03-04 11:10               ` Jon Hunter
2026-03-10  4:44                 ` Akhil R [this message]
2026-03-10  9:47                   ` Jon Hunter
2026-03-02 12:32 ` [PATCH v2 2/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional Akhil R
2026-03-02 20:31   ` Frank Li
2026-03-03 13:27     ` Jon Hunter
2026-03-02 12:32 ` [PATCH v2 3/9] dmaengine: tegra: Make reset control optional Akhil R
2026-03-02 20:31   ` Frank Li
2026-03-02 12:32 ` [PATCH v2 4/9] dmaengine: tegra: Use struct for register offsets Akhil R
2026-03-02 12:32 ` [PATCH v2 5/9] dmaengine: tegra: Support address width > 39 bits Akhil R
2026-03-02 21:14   ` Frank Li
2026-03-02 12:32 ` [PATCH v2 6/9] dmaengine: tegra: Use managed DMA controller registration Akhil R
2026-03-02 12:32 ` [PATCH v2 7/9] dmaengine: tegra: Use iommu-map for stream ID Akhil R
2026-03-02 12:32 ` [PATCH v2 8/9] dmaengine: tegra: Add Tegra264 support Akhil R
2026-03-02 12:32 ` [PATCH v2 9/9] arm64: tegra: Add iommu-map and enable GPCDMA in Tegra264 Akhil R

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