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Tue, 10 Mar 2026 04:36:06 -0700 (PDT) Received: from hu-neersoni-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4637bb1sm12364659b3a.10.2026.03.10.04.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 04:36:05 -0700 (PDT) From: Neeraj Soni To: ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, neeraj.soni@oss.qualcomm.com, Abel Vesa , Abhinaba Rakshit Subject: [PATCH v6 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Date: Tue, 10 Mar 2026 17:05:55 +0530 Message-Id: <20260310113557.348502-2-neeraj.soni@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310113557.348502-1-neeraj.soni@oss.qualcomm.com> References: <20260310113557.348502-1-neeraj.soni@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=H7fWAuYi c=1 sm=1 tr=0 ts=69b00227 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=fvWVRpvV8V6VEHT1R0IA:9 a=OpyuDcXvxspvyRM73sMx:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 8DRoTc6_FBac4kFxaU5GjbDazZFwbNSx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDEwMCBTYWx0ZWRfX9nbV4Yn3WJaJ p/59UgboXZapqPL/1Ebz2W+/cRj0ChJp6BOXw6uZptxg/7zRlcN9Mnc0pv9IzZDLrAd++EMym4c Xtz9Wwy/5wbR0cnCb6EW8Dpyv6Yn4znYdYGXWczMZB5XwG0lxjrcXVXhixfRUgvcXq4YQSosdM/ 6hqGUbNqHuxXCGjaRgpcMXHH5tdcthTdW3KUvRXoLOkloqP0rM0fHrqgl0hMmN745Z40BggW2CL PAvycwQ9TwrDxkITRnrzyjOYfzfhedAksd7iGmVA9MAZYdyFjnXkjYkSRbRGA6+k0EheJCEaV9f tisAh75Yc6wm34wIT4S8Jiv/2W6n4oSFXbekriuMEybk+Nid+3fSA4qfjB9oQRCL49IyKdjka8V P/vZZfxdozwdseHz0rjXtuBIDLJvicz65b6gKLWA/W/Uuc31xz5YXU4Qv/7tRyZt9qGCzGToIYA kISgQWdurJeC0pgXs8A== X-Proofpoint-ORIG-GUID: 8DRoTc6_FBac4kFxaU5GjbDazZFwbNSx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100100 Starting with sc7280(kodiak), the ICE will have its own device-tree node. So add the qcom,ice property to reference it. To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE register region in the SDHCI node. Older SoCs without ICE remain valid as no additional requirement is imposed. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Abhinaba Rakshit Signed-off-by: Abhinaba Rakshit Signed-off-by: Neeraj Soni --- Some initial work is done by Abel here: https://lore.kernel.org/all/ba3da82d-999b-b040-5230-36e60293e0fd@linaro.org/ and by Abhinaba here: https://lore.kernel.org/all/20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-1-2a34d8d03c72@oss.qualcomm.com/ This patch adds the purpose and usage for phandle in the description and encodes it properly in the schema. --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 95 +++++++++++++------ 1 file changed, 67 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 938be8228d66..cc9f7724bdf0 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -140,6 +140,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the Inline Crypto Engine (ICE) hardware block for this controller. + iommus: minItems: 1 maxItems: 8 @@ -193,35 +198,69 @@ allOf: enum: - qcom,sdhci-msm-v4 then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + else: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice unevaluatedProperties: false -- 2.34.1