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Wed, 11 Mar 2026 04:55:12 -0700 (PDT) Received: from rockpi-5b ([45.112.0.200]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-359f01004f7sm5731790a91.0.2026.03.11.04.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 04:55:12 -0700 (PDT) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , FUKAUMI Naoki , Nicolas Frattaroli , Sebastian Reichel , Diederik de Haas , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon , Shawn Lin Subject: [PATCH v1] arm64: dts: rockchip: Enable PCIe CLKREQ# for RK3588 on Rock 5b-5bp-5t series Date: Wed, 11 Mar 2026 17:24:30 +0530 Message-ID: <20260311115502.7353-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add supports-clkreq and the corresponding pinmux configurations for PCIe ASPM L1 substates on the Rock 5B, 5B+, and 5T. The supports-clkreq flag informs the PCIe controller that the hardware routing for the CLKREQ# sideband signal is present. This enables support for PCIe ASPM (Active State Power Management) L1 substates, allowing for better power efficiency. Cc: Shawn Lin Signed-off-by: Anand Moon --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index b3e76ad2d869..668b19c05f7e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay"; @@ -476,7 +477,8 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; @@ -488,7 +490,8 @@ &pcie30phy { &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; base-commit: b29fb8829bff243512bb8c8908fd39406f9fd4c3 -- 2.50.1