Re: [RFC PATCH 5/6] riscv: dts: starfive: jh7110: activate XPbmtUC

[Conor Dooley <conor@kernel.org>]

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On Fri, Mar 13, 2026 at 02:59:44PM -0700, Bo Gan wrote:
> Hi Conor,
> 
> On 3/13/26 06:48, Conor Dooley wrote:
> > On Fri, Mar 13, 2026 at 01:44:06AM -0700, Bo Gan wrote:
> > > Set riscv,xpbmt-uncache-bit to 32 to match SoC memory map:
> > > 
> > >             [0x0,   0x40000000) Low MMIO
> > >      [0x40000000, 0x2_40000000) Cached Mem
> > >    [0x4_40000000, 0x6_40000000) Uncached Mem UC+
> > >    [0x9_00000000, 0x9_d0000000) High MMIO
> > > 
> > > Signed-off-by: Bo Gan <ganboing@gmail.com>
> > 
> > 
> > What I want know is how this whole setup interacts with the existing
> > support that we have for these devices?
> > Samuel's patchetset removed from the devicetree all of the nodes related
> > to having two mappings of the same memory, and modified the existing
> > erratum to only be required for older devicetrees.
> > You've not removed them, only added a new property. The non-coherent
> > peripherals on jh7110 already work prior to this patchset, is there not
> > going to be funky behaviour with both of these things operating in
> > parallel?
> > 
> 
> I just want to clarify that Samuel's change is not touching JH7110, but
> *JH7100*. They are very similar chips, can can confuse people sometimes,
> but JH7110 evolved to put more devices such as gmac/sdio/usb/pcie through
> the front port to make them cache coherent. The left over noncoherent

Believe it or not, I know that! I just misread the filename ;)

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