[RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC"

[Bo Gan <ganboing@gmail.com>]

On platforms that doesn't support Svpbmt or XTheadMae, SoC vendors
sometimes map the system memory twice in physical address space, one
as cached, and the other as uncached. Through the uncached window,
device drivers will be able to map DMA buffer for noncoherent devices.
Such setup is usually found in SoC with pre-Svpbmt Sifive cores.
Make use of such feature by modeling it as "XPbmtUC", a customized
version of Svpbmt, where a single bit in PTE is used for UC control.
There's no IO bit with such scheme, as it's assumed that the PMA
(usually hard-wired on these SoCs) will properly convey the strongly-
ordered, non-idempotent attribute of the MMIO region.

The enablement of such position of "XPbmtUC" is controlled by the
device-tree property "riscv,xpbmt-uncache-bit".

Example:

Starfive JH7110 (Sifive U74):
           [0x0,   0x40000000) Low MMIO
    [0x40000000, 0x2_40000000) Cached Mem
  [0x4_40000000, 0x6_40000000) Uncached Mem UC+
  [0x9_00000000, 0x9_d0000000) High MMIO

Device-tree:
  riscv,xpbmt-uncache-bit = <32>;

Use PTE bit 32 (PPN bit 34) as UC (uncache) control to perfectly
match the memory map of the SoC.

ESWIN EIC770X (Sifive U84/P550):
           [0x0,    0x20000000) Core Internal
    [0x20000000,    0x40000000) Core Internal (Die 1)
    [0x40000000,    0x60000000) Low MMIO
    [0x60000000,    0x80000000) Low MMIO (Die 1)
    [0x80000000, 0x10_80000000) Cached Mem
 [0x20_00000000, 0x30_00000000) Cached Mem (Die 1)
 [0x80_00000000, 0xa0_00000000) High MMIO
 [0xa0_00000000, 0xc0_00000000) High MMIO (Die 1)
 [0xc0_00000000, 0xd0_00000000) Uncached Mem
 [0xe0_00000000, 0xf0_00000000) Uncached Mem (Die 1)

EIC770X is not directly compatible to this model, as the uncached
regions are offsetted, and the offset is different among the Dies
in the dual-die version (EIC7702). so we expect the firmware to
provide a thin layer of hypervisor to transparently re-map:

    [0x80000000,  0x10_80000000) Cached Mem
 [0x20_00000000,  0x30_00000000) Cached Mem (Die 1)
 [0xc0_00000000,  0xd0_00000000) Uncached Mem <----------.
 [0xe0_00000000,  0xf0_00000000) Uncached Mem (Die 1) <--+--.
[0x100_80000000, 0x110_80000000) Mem UC+ ----------------'  |
[0x120_00000000, 0x130_00000000) Mem UC+ (Die 1) -----------'

With that, the firmware/bootloader can set the following at boot:
  riscv,xpbmt-uncache-bit = <38>;

Signed-off-by: Bo Gan <ganboing@gmail.com>
---
 arch/riscv/Kconfig                  | 12 ++++++++++++
 arch/riscv/include/asm/hwcap.h      |  1 +
 arch/riscv/include/asm/pgtable-64.h |  8 ++++++++
 arch/riscv/kernel/cpufeature.c      |  8 ++++++++
 arch/riscv/mm/pgtable.c             |  7 +++++++
 5 files changed, 36 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6b39f37f769a2..f2b4da6a3deb1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -893,6 +893,18 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
 	  versions of clang and GCC to be passed to GAS, which has the same result
 	  as passing zicsr and zifencei to -march.
 
+config RISCV_ISA_XPBMTUC
+	bool "Support XPbmtUC (customized pbmt uncache bit)"
+	depends on 64BIT && MMU
+	depends on RISCV_ALTERNATIVE
+	default n
+	select DMA_DIRECT_REMAP
+	help
+	  Add support for "riscv,xpbmt-uncache-bit" device-tree property.
+	  The bit denotes the bit in PTE that marks the page as uncached.
+
+	  If you don't know what to do here, say N.
+
 config FPU
 	bool "FPU support"
 	default y
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4369a23385413..6baa6566cf4cc 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -111,6 +111,7 @@
 #define RISCV_ISA_EXT_ZILSD		102
 #define RISCV_ISA_EXT_ZCLSD		103
 
+#define RISCV_ISA_EXT_XPBMTUC		126
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
 #define RISCV_ISA_EXT_MAX		128
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 6e789fa58514c..1a6d04884111d 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -140,6 +140,14 @@ enum napot_cont_order {
 #define _PAGE_IO_THEAD		((1UL << 63) | (1UL << 60))
 #define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
 
+#ifdef CONFIG_RISCV_ISA_XPBMTUC
+extern int riscv_xpbmtuc_bit;
+extern u64 riscv_xpbmtuc_mask;
+#endif
+
+#define XPBMTUC_HAS_PAGE_NOCACHE CONFIG_RISCV_ISA_XPBMTUC
+#define XPBMTUC_HAS_PAGE_MTMASK  CONFIG_RISCV_ISA_XPBMTUC
+
 static inline u64 riscv_page_mtmask(void)
 {
 	u64 val;
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fa591aff9d335..faec169004b4a 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -1118,6 +1118,14 @@ void __init riscv_fill_hwcap(void)
 		riscv_v_setup_vsize();
 	}
 
+#ifdef CONFIG_RISCV_ISA_XPBMTUC
+	if (!of_property_read_u32(of_root, "riscv,xpbmt-uncache-bit",
+				  &riscv_xpbmtuc_bit)) {
+		riscv_xpbmtuc_mask = 1UL << riscv_xpbmtuc_bit;
+		set_bit(RISCV_ISA_EXT_XPBMTUC, riscv_isa);
+		pr_info("Using XPbmtUC bit=%d\n", riscv_xpbmtuc_bit);
+	}
+#endif
 	memset(print_str, 0, sizeof(print_str));
 	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 		if (riscv_isa[0] & BIT_MASK(i))
diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
index 807c0a0de1827..4ca442bc8595d 100644
--- a/arch/riscv/mm/pgtable.c
+++ b/arch/riscv/mm/pgtable.c
@@ -5,6 +5,13 @@
 #include <linux/kernel.h>
 #include <linux/pgtable.h>
 
+#ifdef CONFIG_RISCV_ISA_XPBMTUC
+int riscv_xpbmtuc_bit;
+
+u64 riscv_xpbmtuc_mask;
+EXPORT_SYMBOL(riscv_xpbmtuc_mask);
+#endif
+
 int ptep_set_access_flags(struct vm_area_struct *vma,
 			  unsigned long address, pte_t *ptep,
 			  pte_t entry, int dirty)
-- 
2.34.1