[RFC PATCH 6/6] [TESTING-ONLY] riscv: dts: eswin: eic7700: activate XPbmtUC

[Bo Gan <ganboing@gmail.com>]

Set riscv,xpbmt-uncache-bit to 38 for testing only.
(Make sure your firmware remaps it as the following)

            [0x0,    0x20000000) Core Internal
     [0x20000000,    0x40000000) Core Internal (Die 1)
     [0x40000000,    0x60000000) Low MMIO
     [0x60000000,    0x80000000) Low MMIO (Die 1)
     [0x80000000, 0x10_80000000) Cached Mem
  [0x20_00000000, 0x30_00000000) Cached Mem (Die 1)
  [0x80_00000000, 0xa0_00000000) High MMIO
  [0xa0_00000000, 0xc0_00000000) High MMIO (Die 1)
  [0xc0_00000000, 0xd0_00000000) Uncached Mem  <----------.
  [0xe0_00000000, 0xf0_00000000) Uncached Mem (Die 1)  <--+--.
with firmware/hypervisor re-mapping:                      |  |
------------------------------------                      |  |
 [0x100_80000000, 0x110_80000000) Mem UC+ ----------------'  |
 [0x120_00000000, 0x130_00000000) Mem UC+ (Die 1) -----------'

Signed-off-by: Bo Gan <ganboing@gmail.com>
---
 arch/riscv/boot/dts/eswin/eic7700.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index f16ec76fb130c..5c413439daf0a 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -10,6 +10,7 @@
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
+	riscv,xpbmt-uncache-bit = <38>;
 
 	cpus {
 		#address-cells = <1>;
-- 
2.34.1