From: Conor Dooley <conor@kernel.org>
To: Bo Gan <ganboing@gmail.com>
Cc: linux-riscv@lists.infradead.org, samuel.holland@sifive.com,
david@redhat.com, palmer@dabbelt.com, pjw@kernel.org,
gaohan@iscas.ac.cn, me@ziyao.cc, lizhi2@eswincomputing.com,
hal.feng@starfivetech.com, marcel@ziswiler.com, kernel@esmil.dk,
devicetree@vger.kernel.org
Subject: Re: [RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC"
Date: Sun, 15 Mar 2026 12:05:54 +0000 [thread overview]
Message-ID: <20260315-uptight-kinfolk-e4fece4d3447@spud> (raw)
In-Reply-To: <25a8565d-a6bb-401f-b776-d743a2ec9ee0@gmail.com>
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On Fri, Mar 13, 2026 at 02:33:16PM -0700, Bo Gan wrote:
> > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > index fa591aff9d335..faec169004b4a 100644
> > > --- a/arch/riscv/kernel/cpufeature.c
> > > +++ b/arch/riscv/kernel/cpufeature.c
> > > @@ -1118,6 +1118,14 @@ void __init riscv_fill_hwcap(void)
> > > riscv_v_setup_vsize();
> > > }
> > > +#ifdef CONFIG_RISCV_ISA_XPBMTUC
> >
> > Code like this needs to be unconditionally compiled.
> >
> > > + if (!of_property_read_u32(of_root, "riscv,xpbmt-uncache-bit",
> > > + &riscv_xpbmtuc_bit)) {
> > > + riscv_xpbmtuc_mask = 1UL << riscv_xpbmtuc_bit;
> > > + set_bit(RISCV_ISA_EXT_XPBMTUC, riscv_isa);
> > > + pr_info("Using XPbmtUC bit=%d\n", riscv_xpbmtuc_bit);
> > > + }
> > > +#endif
> > > memset(print_str, 0, sizeof(print_str));
> > > for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> > > if (riscv_isa[0] & BIT_MASK(i))
btw, not sure if you saw this comment, about using IS_ENABLED() rather
than ifdeffery.
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next prev parent reply other threads:[~2026-03-15 12:05 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 8:44 [RFC PATCH 0/6] riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC Bo Gan
2026-03-13 8:44 ` [RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC" Bo Gan
2026-03-13 13:24 ` Conor Dooley
2026-03-13 21:33 ` Bo Gan
2026-03-13 23:55 ` Conor Dooley
2026-03-14 0:29 ` Bo Gan
2026-03-14 1:18 ` Conor Dooley
2026-03-14 5:06 ` Bo Gan
2026-03-14 12:17 ` Conor Dooley
2026-03-16 21:22 ` Bo Gan
2026-03-15 12:05 ` Conor Dooley [this message]
2026-03-13 8:44 ` [RFC PATCH 2/6] riscv: alternatives: support auipc+load pair Bo Gan
2026-03-13 8:44 ` [RFC PATCH 3/6] riscv: apply page table attribute bits for XPbmtUC Bo Gan
2026-03-13 13:24 ` Conor Dooley
2026-03-13 21:34 ` Bo Gan
2026-03-13 8:44 ` [RFC PATCH 4/6] riscv: select RISCV_ISA_XPBMTUC in STARFIVE and ESWIN SoC Bo Gan
2026-03-13 13:28 ` Conor Dooley
2026-03-13 21:35 ` Bo Gan
2026-03-13 8:44 ` [RFC PATCH 5/6] riscv: dts: starfive: jh7110: activate XPbmtUC Bo Gan
2026-03-13 13:48 ` Conor Dooley
2026-03-13 21:59 ` Bo Gan
2026-03-13 23:46 ` Conor Dooley
2026-03-13 8:44 ` [RFC PATCH 6/6] [TESTING-ONLY] riscv: dts: eswin: eic7700: " Bo Gan
2026-03-13 12:30 ` [RFC PATCH 0/6] riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC Conor Dooley
2026-03-13 22:17 ` Bo Gan
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