From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE09A3C944A for ; Tue, 17 Mar 2026 13:06:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773752815; cv=none; b=P17HvtHvWri+lmgEBZBbGgGqcpoGXG0PieowUSGbofhu8FOMO1YA19rywQnOvLeC3fQ1bgVRctpJzyJBBIcBnd8BsNdXZ0YdHOgzf5IRk/QwHKcgN6jzCnoPTQza5Zm7K4ob1czZ3j6oQzS8I8qjn/q9VCmaHTobKxyjCoKI4xE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773752815; c=relaxed/simple; bh=koNgmkGi4oFAcsPtky+xnrZgg7RT7H4mBMLj0Q5EbGU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gelDSN8p+27MgdTw7V10JAho9vzrJNl30NseeMsnHDR7nRkos0EhQY4aTOEm1QqdQ5zzGVHZJSdNgJ0ClBEO5BZGenRU7I4ltB9L0UsnYjEe8JL5o/H7m0LwsGEUh7sqp1qvJn3VPX+rWHLJPYdQiFfQgcYIHeoLDat0FxFHdxo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=WLs+1S1I; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="WLs+1S1I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; s=k1; bh=Ah+2nLXC2lBaRkQZlxgJFibBRO1HhXx+HwZXFiGcHrY=; b=WLs+1S 1I8UpyTQ2lBRvc5DEaYYynR0x3WUHcCHviUXcPifKmb/D2xb9rFBGBTDUhK4RnrV xRieXo2AUz20j6IwbQJqRGCjq/Nl5oa2TSR9/SOtz9wEk3zFBGqGmZ88cC1EIFTV InUbAl9nZaSGDKTYmjfQbwpTwiDvjqbPz/5Qlk6CxTrhTiyQjtHnwea78IiIT/q2 As9hM4T+6Wgmi2iFOo/pzIhg7Ib7SIjq14Nmggbu4Hq13Qr88Yughy/Gv8WR6ML5 b9LL0xB6qDRRMrQvBJokBAU8AyQOzHH9VhpXw/yZpeOF57XwXMIUYxGe4nGjYHwf Zmh0j6fTDQFjd6Hw== Received: (qmail 287550 invoked from network); 17 Mar 2026 14:06:49 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 17 Mar 2026 14:06:49 +0100 X-UD-Smtp-Session: l3s3148p1@KYYYAjhN9o8+XdJ7 From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Jassi Brar , Wolfram Sang , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: soc: renesas: add MFIS binding documentation Date: Tue, 17 Mar 2026 14:06:34 +0100 Message-ID: <20260317130638.2804-2-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260317130638.2804-1-wsa+renesas@sang-engineering.com> References: <20260317130638.2804-1-wsa+renesas@sang-engineering.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add device tree bindings for the Renesas Multifunctional Interface (MFIS) as found on the Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW Spinlock/Product Register. Signed-off-by: Wolfram Sang --- Checked with 'dt_bindings_check'. Family-compatible values are not introduced here because MFIS is usually very different per SoC. .../soc/renesas/renesas,r8a78000-mfis.yaml | 160 ++++++++++++++++++ .../mailbox/renesas,r8a78000-mfis.h | 27 +++ 2 files changed, 187 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml create mode 100644 include/dt-bindings/mailbox/renesas,r8a78000-mfis.h diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml new file mode 100644 index 000000000000..dbda28ac781c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MFIS (Multifunctional Interface) controller + +maintainers: + - Wolfram Sang + +description: + Renesas Multifunctional Interface (MFIS) provides functionality for + communication between different CPU cores. Those cores can be in various + domains like AP, RT, or SCP. Functionality includes features like + mailboxes, hardware spinlocks and such. + +properties: + compatible: + enum: + - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR) + - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR) + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: common + - const: mboxes + + interrupts: + minItems: 32 + maxItems: 128 + description: + The interrupts raised by the remote doorbells. + + interrupt-names: + minItems: 32 + maxItems: 128 + items: + pattern: "^ch[0-9]+[ie]$" + description: + An interrupt name is constructed with the prefix 'ch'. Then, the + channel number as specified in the documentation of the SoC. Finally, + the letter 'i' if the interrupt is raised by the IICR register. Or 'e' + if it is raised by the EICR register. + + "#hwlock-cells": + const: 1 + + "#mbox-cells": + const: 2 + description: + The first cell is the channel number as specified in the documentation + of the SoC. The second cell may specify flags as described in the file + . + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#hwlock-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + mfis: syscon@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0x189e0000 0x1000>, <0x18800000 0x40000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + }; diff --git a/include/dt-bindings/mailbox/renesas,r8a78000-mfis.h b/include/dt-bindings/mailbox/renesas,r8a78000-mfis.h new file mode 100644 index 000000000000..89489c2a4847 --- /dev/null +++ b/include/dt-bindings/mailbox/renesas,r8a78000-mfis.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Constants for the mailbox part of the Renesas MFIS IP core. + */ + +#ifndef _DT_BINDINGS_MAILBOX_RENESAS_MFIS_H +#define _DT_BINDINGS_MAILBOX_RENESAS_MFIS_H + +/* + * MFIS HW design before r8a78001 requires a channel to be marked as either + * TX or RX. + */ +#define MFIS_CHANNEL_TX (0 << 0) +#define MFIS_CHANNEL_RX (1 << 0) + +/* + * MFIS variants before r8a78001 work with pairs of IICR and EICR registers. + * Usually, it is specified in the datasheets which of the two a specific core + * should use. Then, it does not need extra description in DT. For plain MFIS + * of r8a78000, this is selectable, though. According to the system design and + * the firmware in use, these channels need to be marked. This is not needed + * with other versions of the MFIS, not even with MFIS-SCP of r8a78000. + */ +#define MFIS_CHANNEL_IICR (0 << 1) +#define MFIS_CHANNEL_EICR (1 << 1) + +#endif -- 2.51.0