From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81])
	(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
	(No client certificate requested)
	by smtp.subspace.kernel.org (Postfix) with ESMTPS id 446A930EF97;
	Thu, 19 Mar 2026 08:02:40 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81
ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
	t=1773907365; cv=none; b=JO9Zk3HF6BnAvlXRxh3Lk0zHzShHYZ74QHse7ejShBCoStaisCS/rRy3CvgRv4Lzei+ExU/Hbvj5A1wuelDGJj115rpuKWKWu2bQ7iy9mmwpHMvCyEMjkQjvmmMuAg2Bx/yYCkhmWnt8W+8cbJyI3l+qbrD3E0Zt9Te5RdlXAkg=
ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org;
	s=arc-20240116; t=1773907365; c=relaxed/simple;
	bh=h0yD8IH+wK2AwJtBvP6hcdTAqqLEEeROY22oW47UUj8=;
	h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:
	 Content-Type:Content-Disposition:In-Reply-To; b=kRI/HZkr+9vmsgpksCrD7Zxr7nO1mFv3cbTBQRydh+ockLZfKoWptrTlZeac6D4NKZPhPqbJiMlcXa4nwS7/M1oxL32jmnQ6iUUUcL6lVGOYekmOwKAU0vzUrJo2epFQmA+2MjIhAqMhDgExuroZ1p1k9pwA816v2X8Z6qG+GZw=
ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=kNnY/Y50; arc=none smtp.client-ip=217.194.8.81
Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it
Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it
Authentication-Results: smtp.subspace.kernel.org;
	dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="kNnY/Y50"
Received: from francesco-nb (93-49-2-63.ip317.fastwebnet.it [93.49.2.63])
	by mail11.truemail.it (Postfix) with ESMTPA id A93231F94A;
	Thu, 19 Mar 2026 09:02:32 +0100 (CET)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it;
	s=default; t=1773907353;
	bh=h0yD8IH+wK2AwJtBvP6hcdTAqqLEEeROY22oW47UUj8=; h=From:To:Subject;
	b=kNnY/Y50A8rFL63mhjwBf0svsePueD2Fg8iR7BnGe8XFetqWnNHnWwPRgLEsDvY/F
	 eb5H7eA6rmjKwnbXeJ0XFYkYQSlZvmv9laXtzMZdsWDMplGtaOAhdJHhcOVL3Qs6XY
	 ANdM0D6Cs38oqT1SDrv8kx17rQkHwTLIixm9XzQvT+8X/ycBF1exWilnMQoAhwZCsc
	 KHRvkAdWbgrP0vC64ZlgaSndfYHrcFYRBLKU7dvKE7/79sSuekt8JQahOP0bRI5yzP
	 eMr7IR0MVjgc29t1Sli7a3aoXRuJW4n9JDHNNsmO2UquzpFTuN0K4rU2YVsR1i00KO
	 I+0/6ehcEILCw==
Date: Thu, 19 Mar 2026 09:02:28 +0100
From: Francesco Dolcini <francesco@dolcini.it>
To: Judith Mendez <jm@ti.com>
Cc: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
	Tero Kristo <kristo@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, Moteen Shah <m-shah@ti.com>,
	Andrew Davis <afd@ti.com>
Subject: Re: [PATCH v2 0/3] Fix MMC pin pull configurations
Message-ID: <20260319080228.GA6079@francesco-nb>
References: <20260223233731.2690472-1-jm@ti.com>
Precedence: bulk
X-Mailing-List: devicetree@vger.kernel.org
List-Id: <devicetree.vger.kernel.org>
List-Subscribe: <mailto:devicetree+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:devicetree+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20260223233731.2690472-1-jm@ti.com>

Hello Judith,

On Mon, Feb 23, 2026 at 05:37:28PM -0600, Judith Mendez wrote:
> This series corrects MMC pin pull-up/pull-down configurations across
> TI AM62L EVM, AM62P SK, & AM62 LP SK boards to properly match their
> hardware design.

On AM62P the first mmc controller has no pinctrl, how is the situation
on this specific interface?

Francesco