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Thu, 19 Mar 2026 03:18:01 -0700 (PDT) From: MidG971 To: shawn.lin@rock-chips.com Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, heiko@sntech.de, jonas@kwiboo.se Subject: Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock Date: Thu, 19 Mar 2026 11:19:11 +0100 Message-Id: <20260319101911.31348-1-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: <7008e941-e4b0-a060-1cd7-55070fd5831f@rock-chips.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable On 2026/03/04, Shawn Lin wrote:=0D > IIUC, you are using Claude to help generate this patch, please=0D > describe it properly, for example,=0D >=0D > Co-developed-by: Claude claude-opus-4-20250514 [1]=0D > or=0D > Assisted-by: Claude:claude-3-opus [2]=0D >=0D > [1] https://lwn.net/Articles/1031473/=0D > [2] https://docs.kernel.org/process/coding-assistants.html=0D =0D Thank you for the guidance. I used Claude as a coding assistant and=0D will use the proper tag in v3:=0D =0D Assisted-by: Claude:claude-3-opus=0D Signed-off-by: MidG971 =0D =0D > There is a missing pipe clock which should be fixed. Please=0D > refer to David's patch[3].=0D >=0D > [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47= 177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1=0D =0D Since our board-level &pcie3x2 override replaces the clocks property=0D entirely, v3 adds CLK_PCIE30X2_PIPE_DFT ("pipe") as well, consistent=0D with David's base DTS patch.=0D =0D I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes=0D successfully and the NVMe device is detected at 15.75 Gb/s. The=0D pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2=0D as its consumer.=0D =0D One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in=0D rk3568-cru.h but was not yet registered in the CRU driver in the=0D tested kernel build, so the pipe clock was excluded from the=0D functional test (pcie3x2 probe fails with -ENOENT at clock index 5=0D when it is included). The gated-fixed-clock node and ref clock were=0D verified working. I expect the pipe clock will work once the CRU=0D driver registers it alongside David's DTS patch.=0D =0D v3 is sent separately.=0D =0D Best regards,=0D MidG971=0D