[PATCH] arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy

[PATCH] arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy

[MidG971]

The PCIe 3.0 PHY requires its power supply regulator to be enabled
before initialization. Without the phy-supply property, the PHY
driver does not ensure the regulator is enabled, causing SRAM
initialization to timeout with "lock failed" errors:

  phy phy-fe8c0000.phy.1: phy poweron failed --> -110
  rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000
  rockchip-pcie fe280000.pcie: phy init failed: -110

This results in NVMe devices in the M.2 slot not being detected.

Add phy-supply referencing vcc3v3_pi6c_03 regulator (which controls
the PI6C PCIe clock generator power via GPIO0_D4) to ensure proper
power sequencing during PHY initialization.

Fixes: 846ef7748fa9 ("arm64: dts: rockchip: Add Radxa ROCK 3B")
Signed-off-by: MidG971 <midgy971@gmail.com>
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Claude <noreply@anthropic.com>
---
 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index c5f67dd6dfd9..a1b2c3d4e5f6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -404,6 +404,7 @@ &pcie2x1 {
 };

 &pcie30phy {
+	phy-supply = <&vcc3v3_pi6c_03>;
 	status = "okay";
 };

--
2.39.5

Re: [PATCH] arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy

[Shawn Lin]

Hi

在 2026/02/13 星期五 23:14, MidG971 写道:
> The PCIe 3.0 PHY requires its power supply regulator to be enabled
> before initialization. Without the phy-supply property, the PHY
> driver does not ensure the regulator is enabled, causing SRAM
> initialization to timeout with "lock failed" errors:
> 
>    phy phy-fe8c0000.phy.1: phy poweron failed --> -110
>    rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000
>    rockchip-pcie fe280000.pcie: phy init failed: -110
> 
> This results in NVMe devices in the M.2 slot not being detected.
> 
> Add phy-supply referencing vcc3v3_pi6c_03 regulator (which controls
> the PI6C PCIe clock generator power via GPIO0_D4) to ensure proper
> power sequencing during PHY initialization.
> 
> Fixes: 846ef7748fa9 ("arm64: dts: rockchip: Add Radxa ROCK 3B")
> Signed-off-by: MidG971 <midgy971@gmail.com>
> Co-developed-by: Claude <noreply@anthropic.com>
> Signed-off-by: Claude <noreply@anthropic.com>

Should put your SOB at last.

> ---
>   arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> index c5f67dd6dfd9..a1b2c3d4e5f6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> @@ -404,6 +404,7 @@ &pcie2x1 {
>   };
> 
>   &pcie30phy {
> +	phy-supply = <&vcc3v3_pi6c_03>;

As a fix which need to be backported, it looks fine for just one-line
change.

However, the whole commit message is misleading. power supply for
pcie30phy is powred up with all other phys' when booting, for instance,
USB, otherwise all IP using PHY should not work, not just PCIe. So 
actually it's not the power but the input refclk, and apprently pi6c
is a 100MHz clock generator which was designed to be a regulator by
mistake in the first place.

If you would like to clean it up later, you could use a 
gated-fixed-clock like:

https://lore.kernel.org/linux-rockchip/35e97a41-b88b-f526-351f-d4c5f70ee4e9@rock-chips.com/T/#u


>   	status = "okay";
>   };
> 
> --
> 2.39.5
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 

Re: [PATCH] arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy

[Jonas Karlman]

Hi,

On 2/13/2026 5:10 PM, Shawn Lin wrote:
> Hi
> 
> 在 2026/02/13 星期五 23:14, MidG971 写道:
>> The PCIe 3.0 PHY requires its power supply regulator to be enabled
>> before initialization. Without the phy-supply property, the PHY
>> driver does not ensure the regulator is enabled, causing SRAM
>> initialization to timeout with "lock failed" errors:

This is incorrect, as already mentioned the ref clock is modeled as a
regulator, and this regulator is both boot-on and always-on and should
not be referenced as the phy-supply, and the reason why I did not do it
in the initial board device tree submission.

>>
>>    phy phy-fe8c0000.phy.1: phy poweron failed --> -110
>>    rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000
>>    rockchip-pcie fe280000.pcie: phy init failed: -110

How did you manage to get this? Did you use wrong/bad boot firmware?

Please try mainline U-Boot for the ROCK 3B target, that will ensure that
both the ref clock "regulator" and the two Ethernet phys are reset
before entering Linux (or other OS) using the mainline Linux device tree
for this board.

>>
>> This results in NVMe devices in the M.2 slot not being detected.
>>
>> Add phy-supply referencing vcc3v3_pi6c_03 regulator (which controls
>> the PI6C PCIe clock generator power via GPIO0_D4) to ensure proper
>> power sequencing during PHY initialization.

As already mentioned, this is not a phy regulator so adding it as a
phy-supply does not correctly reflect the hardware.

>> Fixes: 846ef7748fa9 ("arm64: dts: rockchip: Add Radxa ROCK 3B")
>> Signed-off-by: MidG971 <midgy971@gmail.com>
>> Co-developed-by: Claude <noreply@anthropic.com>
>> Signed-off-by: Claude <noreply@anthropic.com>
> 
> Should put your SOB at last.
> 
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> index c5f67dd6dfd9..a1b2c3d4e5f6 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> @@ -404,6 +404,7 @@ &pcie2x1 {
>>   };
>>
>>   &pcie30phy {
>> +	phy-supply = <&vcc3v3_pi6c_03>;
> 
> As a fix which need to be backported, it looks fine for just one-line
> change.

I disagree, as you mention below, and as mentioned in a comment in the
device tree, the ref clk generator is modeled as a regulator that is
boot-on and always-on that is normally enabled by boot firmware.

> However, the whole commit message is misleading. power supply for
> pcie30phy is powred up with all other phys' when booting, for instance,
> USB, otherwise all IP using PHY should not work, not just PCIe. So 
> actually it's not the power but the input refclk, and apprently pi6c
> is a 100MHz clock generator which was designed to be a regulator by
> mistake in the first place.
> 
> If you would like to clean it up later, you could use a 
> gated-fixed-clock like:

Agree, if anything please re-model the ref clk regulator as a
gated-fixed-clock instead of adding an incorrect phy-supply.

And please try mainline U-Boot targeted for you board if you intend on
using mainline Linux for your board, should most likely fix your PCIe
issue.

Regards,
Jonas

> 
> https://lore.kernel.org/linux-rockchip/35e97a41-b88b-f526-351f-d4c5f70ee4e9@rock-chips.com/T/#u
> 
> 
>>   	status = "okay";
>>   };
>>
>> --
>> 2.39.5

[PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[MidG971]

The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
This chip is currently modeled only as a fixed regulator
(vcc3v3_pi6c_03), with no clock output representation.

The PI6C20100 is a clock generator, not a power supply. Model it
properly as a gated-fixed-clock, following the pattern established
for the Rock 5 ITX and other boards with similar PCIe clock buffer
chips.

The regulator node is kept as-is since it controls the power supply
to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
references this regulator as its vdd-supply and provides a proper
100MHz clock output. The pcie3x2 node is updated to include the
reference clock, matching the approach used in rk3588-rock-5-itx.dts.

Signed-off-by: Claude <noreply@anthropic.com>
Signed-off-by: MidG971 <midgy971@gmail.com>
---

Changes since v1 [1]:
 - Drop phy-supply approach entirely (Jonas, Shawn)
 - Model PI6C20100 as gated-fixed-clock instead
 - Wire reference clock to pcie3x2 controller
 - Follow pattern from rk3588-rock-5-itx.dts

[1] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/

 .../arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index 69001e4..24befc9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -56,7 +56,16 @@
 		};
 	};

-	/* pi6c pcie clock generator */
+	/* PI6C20100 PCIe reference clock buffer (100MHz) */
+	pcie30_refclk: pcie-clock-generator {
+		compatible = "gated-fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "pcie30_refclk";
+		vdd-supply = <&vcc3v3_pi6c_03>;
+	};
+
+	/* PI6C20100 power supply - active-high GPIO0_D4 */
 	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -553,6 +562,13 @@
 };

 &pcie3x2 {
+	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+		 <&cru CLK_PCIE30X2_AUX_NDFT>,
+		 <&pcie30_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk", "aux",
+		      "ref";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie30x2m1_pins>;
 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5

Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Shawn Lin]

在 2026/03/04 星期三 21:29, MidG971 写道:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
> 
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
> 
> The regulator node is kept as-is since it controls the power supply
> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
> references this regulator as its vdd-supply and provides a proper
> 100MHz clock output. The pcie3x2 node is updated to include the
> reference clock, matching the approach used in rk3588-rock-5-itx.dts.
> 
> Signed-off-by: Claude <noreply@anthropic.com>

IIUC, you are using Claude to help generate this patch, please
describe it properly, for example,

Co-developed-by: Claude claude-opus-4-20250514  [1]
or
Assisted-by: Claude:claude-3-opus [2]

[1] https://lwn.net/Articles/1031473/
[2] https://docs.kernel.org/process/coding-assistants.html	

> Signed-off-by: MidG971 <midgy971@gmail.com>
> ---
> 
> Changes since v1 [1]:
>   - Drop phy-supply approach entirely (Jonas, Shawn)
>   - Model PI6C20100 as gated-fixed-clock instead
>   - Wire reference clock to pcie3x2 controller
>   - Follow pattern from rk3588-rock-5-itx.dts
> 
> [1] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
> 
>   .../arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 18 +++++++++++++++++-
>   1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> index 69001e4..24befc9 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> @@ -56,7 +56,16 @@
>   		};
>   	};
> 
> -	/* pi6c pcie clock generator */
> +	/* PI6C20100 PCIe reference clock buffer (100MHz) */
> +	pcie30_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "pcie30_refclk";
> +		vdd-supply = <&vcc3v3_pi6c_03>;
> +	};
> +
> +	/* PI6C20100 power supply - active-high GPIO0_D4 */
>   	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
>   		compatible = "regulator-fixed";
>   		enable-active-high;
> @@ -553,6 +562,13 @@
>   };
> 
>   &pcie3x2 {
> +	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> +		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> +		 <&cru CLK_PCIE30X2_AUX_NDFT>,
> +		 <&pcie30_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk", "aux",
> +		      "ref";

There is a missing pipe clock which should be fixed. Please
refer to David's patch[3].

[3] 
https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1

>   	pinctrl-names = "default";
>   	pinctrl-0 = <&pcie30x2m1_pins>;
>   	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
> --
> 2.39.5
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 

Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[MidG971]

On 2026/03/04, Shawn Lin wrote:
> IIUC, you are using Claude to help generate this patch, please
> describe it properly, for example,
>
> Co-developed-by: Claude claude-opus-4-20250514 [1]
> or
> Assisted-by: Claude:claude-3-opus [2]
>
> [1] https://lwn.net/Articles/1031473/
> [2] https://docs.kernel.org/process/coding-assistants.html

Thank you for the guidance. I used Claude as a coding assistant and
will use the proper tag in v3:

  Assisted-by: Claude:claude-3-opus
  Signed-off-by: MidG971 <midgy971@gmail.com>

> There is a missing pipe clock which should be fixed. Please
> refer to David's patch[3].
>
> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1

Since our board-level &pcie3x2 override replaces the clocks property
entirely, v3 adds CLK_PCIE30X2_PIPE_DFT ("pipe") as well, consistent
with David's base DTS patch.

I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes
successfully and the NVMe device is detected at 15.75 Gb/s. The
pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2
as its consumer.

One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in
rk3568-cru.h but was not yet registered in the CRU driver in the
tested kernel build, so the pipe clock was excluded from the
functional test (pcie3x2 probe fails with -ENOENT at clock index 5
when it is included). The gated-fixed-clock node and ref clock were
verified working. I expect the pipe clock will work once the CRU
driver registers it alongside David's DTS patch.

v3 is sent separately.

Best regards,
MidG971

Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Shawn Lin]

在 2026/03/19 星期四 18:19, MidG971 写道:
> On 2026/03/04, Shawn Lin wrote:
>> IIUC, you are using Claude to help generate this patch, please
>> describe it properly, for example,
>>
>> Co-developed-by: Claude claude-opus-4-20250514 [1]
>> or
>> Assisted-by: Claude:claude-3-opus [2]
>>
>> [1] https://lwn.net/Articles/1031473/
>> [2] https://docs.kernel.org/process/coding-assistants.html
> 
> Thank you for the guidance. I used Claude as a coding assistant and
> will use the proper tag in v3:
> 
>    Assisted-by: Claude:claude-3-opus
>    Signed-off-by: MidG971 <midgy971@gmail.com>
> 
>> There is a missing pipe clock which should be fixed. Please
>> refer to David's patch[3].
>>
>> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
> 
> Since our board-level &pcie3x2 override replaces the clocks property
> entirely, v3 adds CLK_PCIE30X2_PIPE_DFT ("pipe") as well, consistent
> with David's base DTS patch.
> 
> I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes
> successfully and the NVMe device is detected at 15.75 Gb/s. The
> pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2
> as its consumer.
> 
> One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in
> rk3568-cru.h but was not yet registered in the CRU driver in the
> tested kernel build, so the pipe clock was excluded from the
> functional test (pcie3x2 probe fails with -ENOENT at clock index 5
> when it is included). The gated-fixed-clock node and ref clock were
> verified working. I expect the pipe clock will work once the CRU
> driver registers it alongside David's DTS patch.

Pipe clock support was applied and appears in linux-next[1], you could
pick it into your tested kernel build if you'd like to have a try.

[1]https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=41b1a6760959017c4fa1dbc7c3cc318406ab1455

> 
> v3 is sent separately.
> 
> Best regards,
> MidG971
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 

[PATCH v4] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[MidG971]

The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
This chip is currently modeled only as a fixed regulator
(vcc3v3_pi6c_03), with no clock output representation.

The PI6C20100 is a clock generator, not a power supply. Model it
properly as a gated-fixed-clock, following the pattern established
for the Rock 5 ITX and other boards with similar PCIe clock buffer
chips.

The regulator node is kept as-is since it controls the power supply
to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
references this regulator as its vdd-supply and provides a proper
100MHz clock output. The pcie3x2 node is updated to include the
pipe and reference clocks, matching the approach used in
rk3588-rock-5-itx.dts.

Assisted-by: Claude:claude-3-opus
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Midgy BALON <midgy971@gmail.com>
---

Changes since v3 [1]:
 - Add Reviewed-by from Shawn Lin

Changes since v2 [2]:
 - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
 - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
   override (Shawn, referencing David's patch [3])

Changes since v1 [4]:
 - Drop phy-supply approach entirely (Jonas, Shawn)
 - Model PI6C20100 as gated-fixed-clock instead
 - Wire reference clock to pcie3x2 controller
 - Follow pattern from rk3588-rock-5-itx.dts

[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/

 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index c5f67dd6dfd9..1a2b3c4d5e6f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -56,7 +56,16 @@
 		};
 	};

-	/* pi6c pcie clock generator */
+	/* PI6C20100 PCIe reference clock buffer (100MHz) */
+	pcie30_refclk: pcie-clock-generator {
+		compatible = "gated-fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "pcie30_refclk";
+		vdd-supply = <&vcc3v3_pi6c_03>;
+	};
+
+	/* PI6C20100 power supply - active-high GPIO0_D4 */
 	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -553,6 +562,15 @@
 };

 &pcie3x2 {
+	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+		 <&cru CLK_PCIE30X2_AUX_NDFT>,
+		 <&cru CLK_PCIE30X2_PIPE_DFT>,
+		 <&pcie30_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk", "aux",
+		      "pipe", "ref";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie30x2m1_pins>;
 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5

Re: [PATCH v4] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Heiko Stuebner]

Am Donnerstag, 19. März 2026, 15:51:20 Mitteleuropäische Normalzeit schrieb MidG971:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
> 
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
> 
> The regulator node is kept as-is since it controls the power supply
> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
> references this regulator as its vdd-supply and provides a proper
> 100MHz clock output. The pcie3x2 node is updated to include the
> pipe and reference clocks, matching the approach used in
> rk3588-rock-5-itx.dts.
> 
> Assisted-by: Claude:claude-3-opus
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Midgy BALON <midgy971@gmail.com>

Sorry for having to bring up the process again, but the patch
author should match the Signed-off-by line.

You can update the patch author with something like:
  git commit --author="Midgy BALON <midgy971@gmail.com>" --amend

Also is the last name always "UPPER CASE" in your region?

Thanks a lot for staying on this
Heiko


> ---
> 
> Changes since v3 [1]:
>  - Add Reviewed-by from Shawn Lin
> 
> Changes since v2 [2]:
>  - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
>  - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
>    override (Shawn, referencing David's patch [3])
> 
> Changes since v1 [4]:
>  - Drop phy-supply approach entirely (Jonas, Shawn)
>  - Model PI6C20100 as gated-fixed-clock instead
>  - Wire reference clock to pcie3x2 controller
>  - Follow pattern from rk3588-rock-5-itx.dts
> 
> [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
> [2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
> [4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
> 
>  arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> index c5f67dd6dfd9..1a2b3c4d5e6f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> @@ -56,7 +56,16 @@
>  		};
>  	};
> 
> -	/* pi6c pcie clock generator */
> +	/* PI6C20100 PCIe reference clock buffer (100MHz) */
> +	pcie30_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "pcie30_refclk";
> +		vdd-supply = <&vcc3v3_pi6c_03>;
> +	};
> +
> +	/* PI6C20100 power supply - active-high GPIO0_D4 */
>  	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
>  		compatible = "regulator-fixed";
>  		enable-active-high;
> @@ -553,6 +562,15 @@
>  };
> 
>  &pcie3x2 {
> +	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> +		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> +		 <&cru CLK_PCIE30X2_AUX_NDFT>,
> +		 <&cru CLK_PCIE30X2_PIPE_DFT>,
> +		 <&pcie30_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk", "aux",
> +		      "pipe", "ref";
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie30x2m1_pins>;
>  	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
> --
> 2.39.5
> 
> 

[PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[MidG971]

From: Midgy BALON <midgy971@gmail.com>

The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
This chip is currently modeled only as a fixed regulator
(vcc3v3_pi6c_03), with no clock output representation.

The PI6C20100 is a clock generator, not a power supply. Model it
properly as a gated-fixed-clock, following the pattern established
for the Rock 5 ITX and other boards with similar PCIe clock buffer
chips.

The regulator node is kept as-is since it controls the power supply
to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
references this regulator as its vdd-supply and provides a proper
100MHz clock output. The pcie3x2 node is updated to include the
pipe and reference clocks, matching the approach used in
rk3588-rock-5-itx.dts.

Assisted-by: Claude:claude-3-opus
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Midgy BALON <midgy971@gmail.com>
---

Changes since v4:
 - Fix From: line to match Signed-off-by (Heiko)

Changes since v3 [1]:
 - Add Reviewed-by from Shawn Lin

Changes since v2 [2]:
 - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
 - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
   override (Shawn, referencing David's patch [3])

Changes since v1 [4]:
 - Drop phy-supply approach entirely (Jonas, Shawn)
 - Model PI6C20100 as gated-fixed-clock instead
 - Wire reference clock to pcie3x2 controller
 - Follow pattern from rk3588-rock-5-itx.dts

[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/

 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index c5f67dd6dfd9..1a2b3c4d5e6f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -56,7 +56,16 @@
 		};
 	};

-	/* pi6c pcie clock generator */
+	/* PI6C20100 PCIe reference clock buffer (100MHz) */
+	pcie30_refclk: pcie-clock-generator {
+		compatible = "gated-fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "pcie30_refclk";
+		vdd-supply = <&vcc3v3_pi6c_03>;
+	};
+
+	/* PI6C20100 power supply - active-high GPIO0_D4 */
 	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -553,6 +562,15 @@
 };

 &pcie3x2 {
+	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+		 <&cru CLK_PCIE30X2_AUX_NDFT>,
+		 <&cru CLK_PCIE30X2_PIPE_DFT>,
+		 <&pcie30_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk", "aux",
+		      "pipe", "ref";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie30x2m1_pins>;
 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5

Re: [PATCH v4] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Midgy Balon]

Hello Heiko
  > Sorry for having to bring up the process again,
  but the patch
  > author should match the Signed-off-by line.

  Apologies for the inconsistency. I'll fix that in v5.

  > Also is the last name always "UPPER CASE" in your
   region?

  Yes it is standard practice in France to write family names in all
capitals to distinguish them from given names, especially when the
family name could be confused with a given name, not my case but I
comply.

  v5 sent separately.

  Best regards,
  Midgy BALON


Le ven. 20 mars 2026 à 09:48, Heiko Stuebner <heiko@sntech.de> a écrit :
>
> Am Donnerstag, 19. März 2026, 15:51:20 Mitteleuropäische Normalzeit schrieb MidG971:
> > The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> > provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> > This chip is currently modeled only as a fixed regulator
> > (vcc3v3_pi6c_03), with no clock output representation.
> >
> > The PI6C20100 is a clock generator, not a power supply. Model it
> > properly as a gated-fixed-clock, following the pattern established
> > for the Rock 5 ITX and other boards with similar PCIe clock buffer
> > chips.
> >
> > The regulator node is kept as-is since it controls the power supply
> > to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
> > references this regulator as its vdd-supply and provides a proper
> > 100MHz clock output. The pcie3x2 node is updated to include the
> > pipe and reference clocks, matching the approach used in
> > rk3588-rock-5-itx.dts.
> >
> > Assisted-by: Claude:claude-3-opus
> > Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> > Signed-off-by: Midgy BALON <midgy971@gmail.com>
>
> Sorry for having to bring up the process again, but the patch
> author should match the Signed-off-by line.
>
> You can update the patch author with something like:
>   git commit --author="Midgy BALON <midgy971@gmail.com>" --amend
>
> Also is the last name always "UPPER CASE" in your region?
>
> Thanks a lot for staying on this
> Heiko
>
>
> > ---
> >
> > Changes since v3 [1]:
> >  - Add Reviewed-by from Shawn Lin
> >
> > Changes since v2 [2]:
> >  - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
> >  - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
> >    override (Shawn, referencing David's patch [3])
> >
> > Changes since v1 [4]:
> >  - Drop phy-supply approach entirely (Jonas, Shawn)
> >  - Model PI6C20100 as gated-fixed-clock instead
> >  - Wire reference clock to pcie3x2 controller
> >  - Follow pattern from rk3588-rock-5-itx.dts
> >
> > [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
> > [2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
> > [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
> > [4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
> >
> >  arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
> >  1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> > index c5f67dd6dfd9..1a2b3c4d5e6f 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> > @@ -56,7 +56,16 @@
> >               };
> >       };
> >
> > -     /* pi6c pcie clock generator */
> > +     /* PI6C20100 PCIe reference clock buffer (100MHz) */
> > +     pcie30_refclk: pcie-clock-generator {
> > +             compatible = "gated-fixed-clock";
> > +             #clock-cells = <0>;
> > +             clock-frequency = <100000000>;
> > +             clock-output-names = "pcie30_refclk";
> > +             vdd-supply = <&vcc3v3_pi6c_03>;
> > +     };
> > +
> > +     /* PI6C20100 power supply - active-high GPIO0_D4 */
> >       vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
> >               compatible = "regulator-fixed";
> >               enable-active-high;
> > @@ -553,6 +562,15 @@
> >  };
> >
> >  &pcie3x2 {
> > +     clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> > +              <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> > +              <&cru CLK_PCIE30X2_AUX_NDFT>,
> > +              <&cru CLK_PCIE30X2_PIPE_DFT>,
> > +              <&pcie30_refclk>;
> > +     clock-names = "aclk_mst", "aclk_slv",
> > +                   "aclk_dbi", "pclk", "aux",
> > +                   "pipe", "ref";
> >       pinctrl-names = "default";
> >       pinctrl-0 = <&pcie30x2m1_pins>;
> >       reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
> > --
> > 2.39.5
> >
> >
>
>
>
>

Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Heiko Stuebner]

On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
> 
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
      commit: b61f3c69c87b5f061194f413d810723698534b02

As I somehow expected, that AI messed up ;-) .

In the 2nd part of the patch the reported number of lines
in the header (the 15 there) does not match the number of lines
in the diff itself (14). I've fixed that up to not have another
round.

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Jonas Karlman]

Hi Heiko,

On 3/24/2026 6:04 PM, Heiko Stuebner wrote:
> 
> On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
>> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
>> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
>> This chip is currently modeled only as a fixed regulator
>> (vcc3v3_pi6c_03), with no clock output representation.
>>
>> The PI6C20100 is a clock generator, not a power supply. Model it
>> properly as a gated-fixed-clock, following the pattern established
>> for the Rock 5 ITX and other boards with similar PCIe clock buffer
>> chips.
>>
>> [...]
> 
> Applied, thanks!

My comments from v3 [1] was not addressed in v4 och v5. E.g.
regulator-always-on/boot-on not being removed and redundant comments.

[1] https://lore.kernel.org/all/fec0f25d-733a-4b6c-aef1-2ac51bd15798@kwiboo.se/

Regards,
Jonas

> 
> [1/1] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
>       commit: b61f3c69c87b5f061194f413d810723698534b02
> 
> As I somehow expected, that AI messed up ;-) .
> 
> In the 2nd part of the patch the reported number of lines
> in the header (the 15 there) does not match the number of lines
> in the diff itself (14). I've fixed that up to not have another
> round.
> 
> Best regards,

Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Heiko Stuebner]

Hi Jonas,

Am Dienstag, 24. März 2026, 18:15:38 Mitteleuropäische Normalzeit schrieb Jonas Karlman:
> Hi Heiko,
> 
> On 3/24/2026 6:04 PM, Heiko Stuebner wrote:
> > 
> > On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
> >> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> >> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> >> This chip is currently modeled only as a fixed regulator
> >> (vcc3v3_pi6c_03), with no clock output representation.
> >>
> >> The PI6C20100 is a clock generator, not a power supply. Model it
> >> properly as a gated-fixed-clock, following the pattern established
> >> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> >> chips.
> >>
> >> [...]
> > 
> > Applied, thanks!
> 
> My comments from v3 [1] was not addressed in v4 och v5. E.g.
> regulator-always-on/boot-on not being removed and redundant comments.
> 
> [1] https://lore.kernel.org/all/fec0f25d-733a-4b6c-aef1-2ac51bd15798@kwiboo.se/

thank you so much for noticing. Looks like that AI thing is
working "well" ;-) .

I've droped the patch and recreated the for-next branch now.

@Midgy, please honor feedback in future revisions.

Thanks
Heiko

Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Midgy Balon]

Hello Heiko,

I apologize for missing Jonas' comments. It will be done for the next
version as requested.
Indeed Claude works "well" :D . I'll be more careful next time.

Thanks,

Midgy

Le mar. 24 mars 2026 à 23:27, Heiko Stuebner <heiko@sntech.de> a écrit :
>
> Hi Jonas,
>
> Am Dienstag, 24. März 2026, 18:15:38 Mitteleuropäische Normalzeit schrieb Jonas Karlman:
> > Hi Heiko,
> >
> > On 3/24/2026 6:04 PM, Heiko Stuebner wrote:
> > >
> > > On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
> > >> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> > >> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> > >> This chip is currently modeled only as a fixed regulator
> > >> (vcc3v3_pi6c_03), with no clock output representation.
> > >>
> > >> The PI6C20100 is a clock generator, not a power supply. Model it
> > >> properly as a gated-fixed-clock, following the pattern established
> > >> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> > >> chips.
> > >>
> > >> [...]
> > >
> > > Applied, thanks!
> >
> > My comments from v3 [1] was not addressed in v4 och v5. E.g.
> > regulator-always-on/boot-on not being removed and redundant comments.
> >
> > [1] https://lore.kernel.org/all/fec0f25d-733a-4b6c-aef1-2ac51bd15798@kwiboo.se/
>
> thank you so much for noticing. Looks like that AI thing is
> working "well" ;-) .
>
> I've droped the patch and recreated the for-next branch now.
>
> @Midgy, please honor feedback in future revisions.
>
> Thanks
> Heiko
>
>