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Thu, 19 Mar 2026 07:50:27 -0700 (PDT) From: MidG971 To: linux-rockchip@lists.infradead.org Cc: shawn.lin@rock-chips.com, heiko@sntech.de, jonas@kwiboo.se, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, MidG971 Subject: [PATCH v4] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock Date: Thu, 19 Mar 2026 15:51:20 +0100 Message-Id: <20260319145120.99833-1-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260304132957.684616-1-midgy971@gmail.com> References: <20260304132957.684616-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to=0D provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.=0D This chip is currently modeled only as a fixed regulator=0D (vcc3v3_pi6c_03), with no clock output representation.=0D =0D The PI6C20100 is a clock generator, not a power supply. Model it=0D properly as a gated-fixed-clock, following the pattern established=0D for the Rock 5 ITX and other boards with similar PCIe clock buffer=0D chips.=0D =0D The regulator node is kept as-is since it controls the power supply=0D to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node=0D references this regulator as its vdd-supply and provides a proper=0D 100MHz clock output. The pcie3x2 node is updated to include the=0D pipe and reference clocks, matching the approach used in=0D rk3588-rock-5-itx.dts.=0D =0D Assisted-by: Claude:claude-3-opus=0D Reviewed-by: Shawn Lin =0D Signed-off-by: Midgy BALON =0D ---=0D =0D Changes since v3 [1]:=0D - Add Reviewed-by from Shawn Lin=0D =0D Changes since v2 [2]:=0D - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)= =0D - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks=0D override (Shawn, referencing David's patch [3])=0D =0D Changes since v1 [4]:=0D - Drop phy-supply approach entirely (Jonas, Shawn)=0D - Model PI6C20100 as gated-fixed-clock instead=0D - Wire reference clock to pcie3x2 controller=0D - Follow pattern from rk3588-rock-5-itx.dts=0D =0D [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971= @gmail.com/=0D [2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971= @gmail.com/=0D [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee4717= 7829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1=0D [4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971= @gmail.com/=0D =0D arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-= =0D 1 file changed, 20 insertions(+), 1 deletion(-)=0D =0D diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/b= oot/dts/rockchip/rk3568-rock-3b.dts=0D index c5f67dd6dfd9..1a2b3c4d5e6f 100644=0D --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts=0D +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts=0D @@ -56,7 +56,16 @@=0D };=0D };=0D =0D - /* pi6c pcie clock generator */=0D + /* PI6C20100 PCIe reference clock buffer (100MHz) */=0D + pcie30_refclk: pcie-clock-generator {=0D + compatible =3D "gated-fixed-clock";=0D + #clock-cells =3D <0>;=0D + clock-frequency =3D <100000000>;=0D + clock-output-names =3D "pcie30_refclk";=0D + vdd-supply =3D <&vcc3v3_pi6c_03>;=0D + };=0D +=0D + /* PI6C20100 power supply - active-high GPIO0_D4 */=0D vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {=0D compatible =3D "regulator-fixed";=0D enable-active-high;=0D @@ -553,6 +562,15 @@=0D };=0D =0D &pcie3x2 {=0D + clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,=0D + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,=0D + <&cru CLK_PCIE30X2_AUX_NDFT>,=0D + <&cru CLK_PCIE30X2_PIPE_DFT>,=0D + <&pcie30_refclk>;=0D + clock-names =3D "aclk_mst", "aclk_slv",=0D + "aclk_dbi", "pclk", "aux",=0D + "pipe", "ref";=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&pcie30x2m1_pins>;=0D reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;=0D --=0D 2.39.5=0D =0D