On Fri, Mar 20, 2026 at 01:02:04PM +0100, Philipp Zabel wrote: > On Fr, 2026-03-20 at 11:06 +0000, Yixun Lan wrote: > > Instead of grouping several different reset lines into one composite > > reset, decouple them to individual ones which make it more aligned > > with underlying hardware. And for DWC USB driver, it will match well > > with the number of the reset property in the DT bindings. > > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > Also three reset lines each for UCIE and RCPU block. > > Although I can't validate correctness of the id-to-bit assignments, the > changes look consistent. > > I trust that the reason for the grouped reset lines was just > convenience, and not some hardware limitation that requires them to be > controlled at the same time. > > There are no patches using the USB/UCIE/RCPU/PCIE resets found on lore, > so this is not an ABI break. > Eh, I think it's an ABI break either way, but it is being done fast enough that there's no users since this is new as of -rc1. Acked-by: Conor Dooley Just be careful Yixun that U-Boot doesn't import and starting using it, I forget if they use -rc1 or released kernels as their import point. pw-bot: not-applicable Cheers, Conor. > > As an agreement with maintainer, the reset IDs has been rearranged as > > contiguous number but keep most part unchanged to avoid break patches > > which already sent to mailing list. The changes of DT binding header file > > and reset driver are merged together as one single commit to avoid > > git-bisect breakage. > > > > Fixes: 938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver") > > Fixes: 216e0a5e98e5 ("dt-bindings: soc: spacemit: Add K3 reset support and IDs") > > Signed-off-by: Yixun Lan > > Reviewed-by: Philipp Zabel > > If there are no objections, I'll pick this up into reset/fixes for > v7.0-rc6. > > regards > Philipp