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Date: Sat, 21 Mar 2026 17:25:34 +0000
From: Jonathan Cameron <jic23@kernel.org>
To: Chris Morgan <macroalpha82@gmail.com>
Cc: linux-iio@vger.kernel.org, andy@kernel.org, nuno.sa@analog.com,
 dlechner@baylibre.com, jean-baptiste.maneyrol@tdk.com,
 linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
 heiko@sntech.de, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org,
 andriy.shevchenko@intel.com, Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [PATCH V2 3/5] iio: imu: inv_icm42600: Add registers for
 icm42607
Message-ID: <20260321172534.388e71f5@jic23-huawei>
In-Reply-To: <20260319182956.146976-4-macroalpha82@gmail.com>
References: <20260319182956.146976-1-macroalpha82@gmail.com>
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On Thu, 19 Mar 2026 13:29:39 -0500
Chris Morgan <macroalpha82@gmail.com> wrote:

> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Add the register layout for the icm_42607. Most of the registers are
> similar to that of the icm42600, though at different addresses.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Hi Chris,

Just taking a quick look given Jean-Baptiste's concerns
about doing this in the existing driver.

Thanks,

Jonathan

>  
> +/* ICM42607 Specific registers. */
> +
> +/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */
> +
> +/* Register Map for User Bank 0 */
> +#define INV_ICM42607_REG_DEVICE_CONFIG			0x01
> +#define INV_ICM42607_DEVICE_CONFIG_SPI_AP_4WIRE		BIT(2)
> +#define INV_ICM42607_DEVICE_CONFIG_SPI_MODE		BIT(0)
> +
> +#define INV_ICM42607_REG_SIGNAL_PATH_RESET		0x02
> +#define INV_ICM42607_SIGNAL_PATH_RESET_SOFT_RESET	BIT(4)
> +#define INV_ICM42607_SIGNAL_PATH_RESET_FIFO_FLUSH	BIT(2)
> +
> +#define INV_ICM42607_REG_DRIVE_CONFIG1			0x03
> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_DDR_MASK		GENMASK(5, 3)
> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_DDR(_rate)	\
> +FIELD_PREP(INV_ICM42607_DRIVE_CONFIG1_I3C_DDR_MASK, (_rate))

I'd indent the second line of these two line defines to make it easier to
see it's a continuation.

> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_SDR_MASK		GENMASK(2, 0)
> +#define INV_ICM42607_DRIVE_CONFIG1_I3C_SDR(_rate)	\
> +FIELD_PREP(INV_ICM42607_DRIVE_CONFIG1_I3C_SDR_MASK, (_rate))